Integrated circuit defect review and classification process

• US 6,654,114 B2
• Filed: 08/05/2002
• Issued: 11/25/2003
• Est. Priority Date: 01/30/1997
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Zeimantz, Lisa R.
• Primary Examiner(s): Pham, Hoa Q.
• Application Number:
  US10/213,129
• Publication Number:
  US 20020191181A1
• Time in Patent Office: 477 Days
• Field of Search: 356/237.1, 356/237.2, 356/237.3, 356/237.4, 356/237.5, 356/239.1, 356/239.3, 356/239.7, 356/239.8, 356/394, 356/429-431, 250/307, 250/310
• US Class Current: 356/237.4
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: H01L 2223/5444 for electrical read out

Abstract

The present invention relates to circuit defect detection, classification, and review in the wafer stage of the integrated circuit semiconductor device manufacturing process. The method of processing integrated circuit semiconductor dice on a wafer in a manufacturing process for dice comprises the steps of visually inspecting the dice on the wafer to determine defects thereon, summarizing the number, types, and ranges of sizes of the defects of the dice on the wafer, and determining if the wafer is acceptable to proceed in the manufacturing process.

Claims

1. A defect review method for a plurality of wafers in a process, each wafer of the plurality of wafers having integrated circuit semiconductor dice thereon, each integrated circuit semiconductor die of said integrated circuit semiconductor dice having a plurality of circuits, said method comprising:

determining from historical information concerning at least one process of manufacture of integrated circuit semiconductor dice on wafers at least one relationship between at least one type of surface defect on a plurality of said integrated circuit semiconductor dice on said wafers, said at least one type of surface defect visible to a user visually inspecting said integrated circuit semiconductor dice on said wafers for a surface defect thereon and determining at least one subsequent failure of a plurality of dice having a surface defect thereon of said integrated circuit semiconductor dice on said wafers;

visually inspecting a plurality of dice of integrated circuit semiconductor dice on a wafer to determine surface defects thereon by a user viewing said plurality of dice of said integrated circuit semiconductor dice on said wafer, said surface defects including at least one defect of defects from bond pad formation and from incomplete formation of said at least one plurality of circuits of each of said plurality of dice of said integrated circuit semiconductor dice on said wafer, said visually inspecting said plurality of dice of said integrated circuit semiconductor dice on said wafer including said user using one of a scanning electron microscope and an optical microscope;

selecting types of surface defects present on said plurality of dice of said integrated circuit semiconductor dice on said wafer from said visual inspection;

selecting a range of sizes of said surface defects from said visual inspection of said plurality of dice of said integrated circuit semiconductor dice on said wafer by said user;

selecting a number of said integrated circuit semiconductor dice for visual inspection on said wafer by said user selecting at least one other die of said integrated circuit semiconductor dice on said wafer for visual inspection thereof for surface defects thereon;

summarizing said number, types, and range of sizes of said surface defects of said plurality of dice and said at least one other die of said integrated circuit semiconductor dice on said wafer from a visual inspection of at least four dice of said integrated circuit semiconductor dice on said wafer by said user;

comparing said number, types and ranges of sizes of said surface defects of said plurality of dice and said at least one other die of said integrated circuit semiconductor dice on said wafer to said historical information concerning said at least one process of manufacture of integrated circuit semiconductor dice on wafers; and

determining if said wafer is acceptable to proceed in said process of manufacture based upon said visual inspection of said at least four dice of said integrated circuit semiconductor dice on said wafer by said user and based upon said historical information concerning said at least one process of manufacture of integrated circuit semiconductor dice on wafers and said at least one relationship between said at least one type of surface defect on said plurality of dice of said integrated circuit semiconductor dice on said wafers visible to said user visually inspecting said integrated circuit semiconductor dice on said wafers and said at least one subsequent failure of said plurality of dice having said surface defect thereon of said integrated circuit semiconductor dice on said wafers.

2. A defect review process for integrated circuit semiconductor dice on a wafer in a process for said integrated circuit semiconductor dice, each integrated circuit semiconductor die of said integrated circuit semiconductor dice having at least one circuit, said process comprising:

determining from historical information concerning a process for integrated circuit semiconductor dice on wafers at least one relationship between at least one type of surface defect on at least more than two dice of said integrated circuit semiconductor dice on said wafers, said at least one type of surface defect visible to a user visually inspecting said integrated circuit semiconductor dice on said wafers for at least one surface defect thereon and determining at least one subsequent failure of more than two dice having a surface defect thereon of said integrated circuit semiconductor dice on said wafers;

visually inspecting said integrated circuit semiconductor dice on said wafer to determine surface defects thereon by said user visually inspecting more than two dice of said integrated circuit semiconductor dice on said wafer, said surface defects including at least one defect of defects from bond pad formation and from incomplete formation of said at least one circuit of each of said more than two dice of said integrated circuit semiconductor dice on said wafer, said visually inspecting said more than two dice of said integrated circuit semiconductor dice on said wafer including said user using one of a scanning electron microscope and an optical microscope;

classifying visual surface defects on said integrated circuit semiconductor dice of said wafer as to type and range of size of surface defect by said user from a manual visual inspection of said more than two dice of said integrated circuit semiconductor dice on said wafer;

determining a number of sid surface defects on said integrated circuit semiconductor dice on said wafer;

selecting a range of sizes of said surface defects from said visual inspection of said more than two dice of said integrated circuit semiconductor dice on said wafer by said user;

selecting a number of said integrated circuit dice for visual inspection on said wafer by said user selecting at least one other die of said integrated circuit semiconductor dice on said wafer for visual inspection thereof for surface defects thereon;

summarizing said number, types, and range of sizes of said surface defects on said integrated circuit semiconductor dice on said wafer by said user from said visual inspection of said more than two dice of said integrated circuit semiconductor dice on said wafer;

comparing said number, types and ranges of sizes of said surface defects of said more than two dice and said at least one other die of said integrated circuit semiconductor dice on said wafer to said historical information concerning said process for integrated circuit semiconductor dice on wafers;

determining if said wafer is acceptable to proceed in said process from a visual inspection of more than three dice of said integrated circuit semiconductor dice on said wafer by said user and based upon said historical information concerning said process for integrated circuit semiconductor dice on wafers and said at least one relationship between said at least one type of surface defect on said at least two dice of said integrated circuit semiconductor dice on said wafers visible to said user visually inspecting said integrated circuit semiconductor dice on said wafers and said at least one subsequent failure of said at least one die having said surface defect thereon of said integrated circuit semiconductor dice on said wafers; and

photographing said surface defects on said integrated circuit semiconductor dice of said wafer from said visual inspection of said more than two dice of said integrated circuit semiconductor dice on said wafer by said user.

3. The process of claim 2, further including:

classifying visual surface defects of said more than two dice of said integrated circuit semiconductor dice of said wafer as to size of said visual surface defect.

4. The process of claim 3, further including:

classifying said visual surface defects of said more than two dice of said integrated circuit semiconductor dice of said wafer as to a size range of said visual surface defect.

5. The process of claim 4, further including:

summarizing the number, types, and range of sizes of said visual surface defects of said more than two dice of said integrated circuit semiconductor dice on said wafer in a tabular manner.

6. The process of claim 5, further including:

summarizing the number, types, and range of sizes of said visual surface defects of said more than two dice of said integrated circuit semiconductor dice on said wafer in a display of said integrated circuit semiconductor dice of said wafer.

7. The process of claim 2, further including:

determining if said wafer is acceptable to proceed in said process as a wafer being processed with other wafers having dice thereon as a group of wafers in said process.

8. The process of claim 2, further including:

determining if an individual die of said more than two dice of said integrated circuit semiconductor dice of said wafer is acceptable to proceed in said process.

9. A defect review method for integrated circuit semiconductor dice on a wafer in a process for said integrated circuit semiconductor dice, each integrated circuit semiconductor die of said integrated circuit semiconductor dice having a plurality of circuits, said method comprising:

determining from historical information concerning a process for integrated circuit semiconductor dice on wafers at least one relationship between at least one type of surface defect on more than two dice of said integrated circuit semiconductor dice on said wafers, said at least one type of surface defect visible to a user visually inspecting said integrated circuit semiconductor dice on said wafers for at least one surface defect thereon and determining at least one subsequent failure of more than two dice having a surface defect thereon of said integrated circuit semiconductor dice on said wafers;

selecting types of surface defects to be determined from said visual inspection of said integrated circuit semiconductor dice on said wafer by said user visually inspecting said more than two dice of said integrated circuit semiconductor dice on said wafer, said surface defects including at least one defect of defects from bond pad formation and from incomplete formation of said plurality of circuits of each of said integrated circuit semiconductor dice;

selecting a range of sizes of said surface defects to be determined from said visual inspection of said integrated circuit semiconductor dice on said wafer by said user from said visual inspection of said more than two dice of said integrated circuit semiconductor dice on said wafer;

selecting a number of said integrated circuit semiconductor dice for visual inspection on said wafer by said user from said visual inspection of said more than two dice of said integrated circuit semiconductor dice on said wafer;

visually inspecting at least one other integrated circuit semiconductor die of said integrated circuit semiconductor dice on said wafer to determine surface defects thereon by said user, said visually inspecting said more than two dice of said integrated circuit semiconductor dice on said wafer including said user using one of a scanning electron microscope and an optical microscope;

summarizing number, types, and range of sizes of said surface defects of said integrated circuit semiconductor dice on said wafer by said user from a visual inspection of at least three dice of said integrated circuit semiconductor dice on said wafer;

comparing said number, types and range of sizes of said surface defects of said more than two dice and said at least one other die of said integrated circuit semiconductor dice on said wafer to said historical information concerning said process for integrated circuit semiconductor dice on wafers; and

determining if said wafer is acceptable to proceed in said process from said visual inspection of said at least three dice of said integrated circuit semiconductor dice on said wafer and based upon said historical information concerning said process for integrated circuit semiconductor dice on wafers and said at least one relationship between said at least one type of surface defect on said more than two dice of said integrated circuit semiconductor dice on said wafers visible to said user visually inspecting said integrated circuit semiconductor dice on said wafers and said at least one subsequent failure of said more than two dice having said surface defect thereon of said integrated circuit semiconductor dice on said wafers.

10. A method for processing of wafers having at least one integrated circuit semiconductor die thereon for determining defects in a process for said wafers, said at least one integrated circuit semiconductor die having a plurality of circuits, said method comprising:

determining from historical information concerning a process for integrated circuit semiconductor dice on wafers at least one relationship between at least one type of surface defect on more than two dice of said integrated circuit semiconductor dice on said wafers, the at least one type of surface defect visible to a user visually inspecting said integrated circuit semiconductor dice on said wafers for at least one surface defect thereon and determining at least one subsequent failure of more than two dice having a surface defect thereon of said integrated circuit semiconductor dice on said wafers;

selecting types of surface defects to be determined from a visual inspection of said integrated circuit semiconductor dice on said wafer by said user visually inspecting more than two dice of said integrated circuit semiconductor dice on said wafer, said types of surface defects including at least one surface defect of surface defects from bond pad formation and defects from incomplete formation of said plurality of circuits of said each integrated circuit semiconductor die of said integrated circuit semiconductor dice on said wafer;

selecting a range of sizes of said surface defects to be determined from said visual inspection of said integrated circuit semiconductor dice on said wafer by said user from said visual inspection of said more than two dice of said integrated circuit semiconductor dice on said wafer;

selecting a number of said integrated circuit semiconductor dice for visual inspection on said wafer by said user from said visual inspection of said more than two dice of said integrated circuit semiconductor dice on said wafer;

visually inspecting said integrated circuit semiconductor dice on said wafer to determine surface defects thereon by said user visually inspecting said more than two dice of said integrated circuit semiconductor dice on said wafer, wherein said visual inspection of said more than two dice of said integrated circuit semiconductor dice on said wafer includes using an apparatus for viewing said integrated circuit semiconductor dice;

summarizing number, types, and range of sizes of said surface defects of said integrated circuit semiconductor dice on said wafer by said user from said visual inspection of said more than two dice of said integrated circuit semiconductor dice on said wafer;

comparing said number, types and range of sizes of said surface defects of said more than two dice and at least one other die of said integrated circuit semiconductor dice on said wafer to said historical information concerning said process for said integrated circuit semiconductor dice on wafers; and

determining if said wafer is acceptable to proceed in said process based upon said visual inspection by said user of said more than two dice on said wafer and based upon said historical information concerning said process for integrated circuit semiconductor dice on wafers and said at least one relationship between the at least one type of surface defect on said more than two dice of said integrated circuit semiconductor dice on the wafers visible to the user visually inspecting the integrated circuit semiconductor dice on said wafers and the at least one subsequent failure of said more than two dice having said surface defect thereon of said integrated circuit semiconductor dice on said wafers.

11. A method of determining defects for integrated circuit semiconductor dice on a wafer in a process for said integrated circuit semiconductor dice by a user, each integrated circuit semiconductor die of said integrated circuit semiconductor dice having a plurality of circuits, said method comprising:

determining from information concerning a process of manufacture of integrated circuit semiconductor dice on wafers relationships between at least two types of surface defects on at least two dice of said integrated circuit semiconductor dice on said wafers, said at least two types of surface defects visible to a user visually inspecting said integrated circuit semiconductor dice on said wafers for said at least two types of surface defects thereon and determining at least one subsequent failure of at least one die having a surface defect thereon of said integrated circuit semiconductor dice on said wafers;

selecting types of surface defects to be determined from a visual inspection of said integrated circuit semiconductor dice on said wafer by said user visually inspecting more than two dice of said integrated circuit semiconductor dice on said wafer, said surface defects including at least one surface defect of surface defects from bond pad formation and from incomplete formation of said plurality of circuits of said each integrated circuit semiconductor die of said integrated circuit semiconductor dice on said wafer, said visual inspection of said more than two dice of said integrated circuit semiconductor dice on said wafer including said user using one of a scanning electron microscope and an optical microscope;

selecting a size of said surface defects to be determined from said visual inspection of said integrated circuit semiconductor dice on said wafer by said user visually inspecting said more than two dice of said integrated circuit semiconductor dice on said wafer;

selecting a number of said integrated circuit semiconductor dice for visual inspection on said wafer by said user based on said visual inspection of said more than two dice of said integrated circuit semiconductor dice on said wafer;

visually inspecting at least one other die of said integrated circuit semiconductor dice on said wafer to determine surface defects thereon by said user;

summarizing number, types, and size of said surface defects of said integrated circuit semiconductor dice on said wafer by said user from a visual inspection of at least three dice of said integrated circuit semiconductor dice on said wafer;

comparing said number, types and size of said surface defects of said more than two dice and said at least one other die of said integrated circuit semiconductor dice on said wafer to said historical information concerning said process of manufacture for said integrated circuit semiconductor dice on wafers;

determining if said wafer is acceptable to proceed in said process of manufacture from said visual inspection of said at least three dice of said integrated circuit semiconductor dice on said wafer and based upon said historical information concerning said process of manufacture for integrated circuit semiconductor dice on wafers and said relationships between said at least two types of surface defects on said more than two dice of said integrated circuit semiconductor dice on said wafers visible to said user visually inspecting said integrated circuit semiconductor dice on said wafers and said at least one subsequent failure of said at least one die having said surface defect thereon of said integrated circuit semiconductor dice on said wafers; and

photographing said surface defects on said integrated circuit semiconductor dice of said wafer from said visual inspection by said user of said more than two dice of said integrated circuit semiconductor dice on said wafer.

12. The method of claim 11, further including:

classifying visual surface defects of said integrated circuit semiconductor dice of said wafer as to type of surface defect.

13. The method of claim 12, further including:

classifying said visual surface defects of said integrated circuit semiconductor dice of said wafer as to size of said visual surface defects.

14. The method of claim 13, further including:

classifying said visual surface defects of said integrated circuit semiconductor dice of said wafer as to a size range of said visual surface defects.

15. The method of claim 14, further including:

summarizing said number, types, and range of sizes of said visual surface defects of said integrated circuit semiconductor dice on said wafer in a tabular manner.

16. The method of claim 15, further including:

summarizing said number, types, and range of sizes of said visual surface defects of said integrated circuit semiconductor dice on said wafer in a display of said integrated circuit semiconductor dice of said wafer.

17. The method of claim 11, further including:

determining if said wafer is acceptable to proceed in said process of manufacture as a wafer being processed with other wafers having integrated circuit semiconductor dice thereon as a group of wafers in said process of manufacture.

18. The method of claim 11, further including:

determining if an individual die of said integrated circuit semiconductor dice of said wafer is acceptable to proceed in said process of manufacture.

19. A method for determining defects of integrated circuit semiconductor dice on a wafer in a process for said integrated circuit semiconductor dice by a user, each integrated circuit semiconductor die of said integrated circuit semiconductor dice having a plurality of circuits, said method comprising:

determining from historical information concerning a process of manufacture of integrated circuit semiconductor dice on wafers at least one relationship between at least one type of surface defect on more than two integrated circuit semiconductor dice of said integrated circuit semiconductor dice on said wafers, said at least one type of surface defect visible to a user visually inspecting said integrated circuit semiconductor dice on said wafers for at least one surface defect thereon and determining at least one subsequent failure of at least one integrated circuit semiconductor die having a surface defect thereon of said integrated circuit semiconductor dice on said wafers, said visual inspection of said more than two dice of said integrated circuit semiconductor dice on said wafer by said user including said user operating one of a scanning electron microscope and an optical microscope;

visually inspecting more than two dice of said integrated circuit semiconductor dice on said wafer to determine surface defects thereon by said user, said surface defects including at least one surface defect of surface defects from bond pad formation and from incomplete formation of said plurality of circuits of said each integrated circuit semiconductor die of said integrated circuit semiconductor dice on said wafer, said surface defects having a type and size;

summarizing the surface defects on said integrated circuit semiconductor dice on said wafer by said user from said visual inspection of said more than two dice of said integrated circuit semiconductor dice on said wafer;

comparing number, types and ranges of sizes of said surface defects of at least one integrated circuit semiconductor die and at least one other integrated circuit semiconductor die of said integrated circuit semiconductor dice on said wafer to said historical information concerning said process of manufacture of integrated circuit semiconductor dice on wafers; and

determining if said wafer is acceptable to proceed in said process of manufacture from said visual inspection of said more than two dice of said integrated circuit semiconductor dice on said wafer and based upon said historical information concerning said process of manufacture for integrated circuit semiconductor dice on wafers and said at least one relationship between said at least one type of surface defect on said more than two dice of said integrated circuit semiconductor dice on said wafers visible to said user visually inspecting said integrated circuit semiconductor dice on said wafers and said at least one subsequent failure of said at least two dice having said surface defect thereon of said integrated circuit semiconductor dice on said wafers.

20. The method of claim 19, further comprising:

selecting types of said surface defects to be determined from said visual inspection of said integrated circuit semiconductor dice on said wafer by said user from a visual inspection of at least three integrated circuit semiconductor dice of said integrated circuit semiconductor dice on said wafer;

selecting sizes of said surface defects to be determined from said visual inspection of said at least three integrated circuit semiconductor dice of said integrated circuit semiconductor dice on said wafer; and

selecting at least three of said integrated circuit semiconductor dice for visual inspection on said wafer from said visual inspection of at least three dice of said integrated circuit semiconductor dice on said wafer.

21. The method of claim 19, wherein said visually inspecting said integrated circuit semiconductor dice on said wafer includes using a scanning electron microscope or optical microscope by said user.