Magnetoresistance random access memory

• US 6,654,278 B1
• Filed: 07/31/2002
• Issued: 11/25/2003
• Est. Priority Date: 07/31/2002
• Status: Expired due to Fees

• Current Assignee: Everspin Technologies Incorporated
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Engel, Bradley N., Janesky, Jason Allen
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US10/209,156
• Time in Patent Office: 482 Days
• Field of Search: 365/158, 365/171, 365/173, 365/157
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods

Abstract

A magnetoresistive tunneling junction memory cell comprises a magnetoresistive tunneling barrier (16), a bit magnetic region (15), a reference magnetic region (17), and current lines (20, 30) for inducing an applied magnetic field in the bit and reference magnetic regions. The bit magnetic region has a bit magnetic moment (43, 40,1425, 1625, 1950, 2315) that has a polarity in a bit easy axis (59, 1435) when there is no applied magnetic field. The tunneling barrier and the bit and reference magnetic regions form a magnetoresistive tunneling junction device (10, 72, 73, 74, 75, 76). In some implementations (73, 74, 75), the reference magnetic region has a reference magnetic moment (40, 1430, 1440, 1920, 1925) that is non-parallel to the bit easy axis. In other implementations (76), the reference magnetic region has a magnetization vortex (2310) with a net reference magnetic moment that is essentially zero. An applied magnetic field changes the magnetic state of the reference magnetic region such that the magnetic state of the bit magnetic region can be determined by a magnetoresistive measurement.

Claims

1. A magnetoresistive tunneling junction memory cell comprising:

an electrically insulating material designed to form a magnetoresistive tunneling barrier;

a bit magnetic region positioned on one side of the electrically insulating material, the bit magnetic region having a bit magnetic moment that has a polarity in a bit easy axis when there is no applied magnetic field;

a reference magnetic region positioned on an opposite side of the electrically insulating material, wherein the electrically insulating material and the bit and reference magnetic regions form a magnetoresistive tunneling junction device (MTJD); and

means for inducing an applied magnetic field in the bit and reference magnetic regions;

wherein the reference magnetic region has a low aspect ratio and has a reference magnetic moment that is substantially orthogonal to the bit easy axis when the applied magnetic field has a magnitude of zero, at which magnitude the MTJD has a reference magnetoresistance, and

wherein the polarity of the bit magnetic moment is reliably indicated by a sign of a change of the magnetoresistance of the MTJD from a rotation of the reference magnetic moment, and the polarity of the bit magnetic moment is not switched, when the applied magnetic field has a sense value that is within a non-switching magnetic field region.

2. The magnetoresistive tunneling junction memory cell according to claim 1, wherein the reference magnetic region comprises a pinned magnetic layer for providing the reference magnetic moment, comprising:

a ferromagnetic layer that is adjacent to the electrically insulating material; and

an anti-ferromagnetic layer adjacent to the ferromagnetic layer.

3. The magnetoresistive tunneling junction memory cell according to claim 1, wherein the reference magnetic region comprises:

a pinning anti-ferromagnetic layer that has a pinning direction orthogonal to the bit easy axis; and

a synthetic anti-ferromagnetic layer (SAF) that is adjacent to the pinning anti-ferromagnetic layer and the electrically insulating material, and provides the reference magnetic moment,

wherein the reference magnetic moment has a rotational response strength such that the reference magnetic moment is rotated by the applied magnetic field having the sense value, and wherein the rotational response strength is determined by a combination of a coupling layer strength in the SAF, magnetic anisotropy and a moment imbalance of ferromagnetic layers of the SAF.

4. The magnetoresistive tunneling junction memory cell according to claim 3, wherein the SAF comprises N ferromagnetic layers which are anti-ferromagnetically coupled, where N is an integer number greater than or equal to two.

5. The magnetoresistive tunneling junction memory cell according to claim 1, wherein an aspect ratio of the reference magnetic region is between 0.6 and 1.4.

6. The magnetoresistive tunneling junction memory cell according to claim 5, wherein an aspect ratio of the reference magnetic region is between 0.8 and 1.2.

7. The magnetoresistive tunneling junction memory cell according to claim 6, wherein the means for inducing an applied magnetic field in the bit and reference magnetic regions comprises:

a word line passing near one of the bit and reference magnetic regions; and

a digit line orthogonal to the word line and passing near the other of the bit and reference magnetic regions,

wherein the word and digit lines are oriented substantially 45 degrees with respect to the bit easy axis.

8. The magnetoresistive tunneling junction memory cell according to claim 7, wherein the means for inducing an applied magnetic field in the bit and reference magnetic regions further comprises a read line passing near the reference magnetic region.

9. The magnetoresistive tunneling junction memory cell according to claim 6, wherein the means for inducing an applied magnetic field in the bit and reference magnetic regions comprises:

a word line passing near one of the bit and reference magnetic regions; and

a digit line orthogonal to the word line and passing near the other of the bit and reference magnetic regions,

wherein one of the word and digit lines is oriented substantially orthogonal to the bit easy axis.

10. The magnetoresistive tunneling junction memory cell according to claim 1, wherein the bit magnetic region comprises N ferromagnetic layers which are anti-ferromagnetically coupled, where N is an integer number greater than or equal to two.

11. An integrated circuit comprising the magnetoresistive tunneling junction memory cell according to claim 1.

12. An electro-optical equipment comprising the magnetoresistive tunneling junction memory cell according to claim 1.

13. A magnetoresistive tunneling junction memory cell comprising:

an electrically insulating material designed to form a magnetoresistive tunneling barrier;

a bit magnetic region positioned on one side of the electrically insulating material, the bit magnetic region having a bit magnetic moment that has a polarity in a bit easy axis when there is no applied magnetic field;

a reference magnetic region positioned on an opposite side of the , wherein the electrically insulating material and the bit and reference magnetic regions form a magnetoresistive tunneling junction device (MTJD); and

a means for inducing an applied magnetic field in the bit and reference magnetic regions,

wherein the reference magnetic region has a reference magnetic moment that has two stable positions generated by an anisotropy of the reference magnetic region at approximately equal angles from an orthogonal to the bit easy axis when the applied magnetic field has a magnitude of zero, and

wherein the polarity of the bit magnetic moment is reliably indicated by a sign of a change of a magnetoresistance of the MTJD and the polarity of the bit magnetic moment is not switched when a component of the applied magnetic field is changed from a first polarity to a second polarity in the bit easy axis while the applied magnetic field has a sense value that is within a non-switching magnetic field region.

14. The magnetoresistive tunneling junction memory cell according to claim 13, wherein the anisotropy is generated by an aspect ratio of the reference magnetic region that is greater than 1.

15. The magnetoresistive tunneling junction memory cell according to claim 13, wherein the anisotropy is generated by an aspect ratio of the reference magnetic region that is between 1.5 and 3.0.

16. The magnetoresistive tunneling junction memory cell according to claim 13, wherein the reference magnetic region comprises:

a pinning anti-ferromagnetic layer that has a pinning direction that is orthogonal to the bit easy axis; and

a synthetic anti-ferromagnetic layer (SAF) that is adjacent to the pinning anti-ferromagnetic layer and the electrically insulating material, and provides the reference magnetic moment based on the anisotropy and a combination of the pinning direction and a strength of a coupling layer of the SAF.

17. The magnetoresistive tunneling junction memory cell according to claim 16, wherein the anisotropy is at least partially generated by induced magnetic anisotrpy properties of a ferromagnetic layer of the SAF that is adjacent to the electrically insulating material.

18. The magnetoresistive tunneling junction memory cell according to claim 16, wherein the anisotropy is generated by an aspect ratio of the reference magnetic region that is greater than 1.

19. The magnetoresistive tunneling junction memory cell according to claim 18, wherein the anisotropy is generated by an aspect ratio of the reference magnetic region that is between 1.5 and 3.0.

20. The magnetoresistive tunneling junction memory cell according to claim 13, wherein the bit magnetic region comprises N ferromagnetic layers which are anti-ferromagnetically coupled, where N is an integer number greater than or equal to two, and each layer has a thickness.

21. The magnetoresistive tunneling junction memory cell according to claim 13, wherein the means for inducing an applied magnetic field in the bit and reference magnetic regions comprises:

a word line passing near one of the bit and reference magnetic regions; and

a digit line orthogonal to the word line and passing near the other of the bit and reference magnetic regions,

wherein the word and digit lines are oriented substantially 45 degrees with respect to the bit easy axis.

22. The magnetoresistive tunneling junction memory cell according to claim 21, wherein the means for inducing an applied magnetic field in the bit and reference magnetic regions further comprises a read line passing near the reference magnetic region.

23. The magnetoresistive tunneling junction memory cell according to claim 13, wherein the means for inducing an applied magnetic field in the bit and reference magnetic regions comprises:

a word line passing near one of the bit and reference magnetic regions; and

a digit line orthogonal to the word line and passing near the other of the bit and reference magnetic regions,

wherein one of the word and digit lines is oriented substantially orthogonal to the bit easy axis.

24. An integrated circuit comprising the magnetoresistive tunneling junction memory cell according to claim 13.

25. An electro-optical equipment comprising the magnetoresistive tunneling junction memory cell according to claim 13.

26. A magnetoresistive tunneling junction memory cell comprising:

an electrically insulating material designed to form a magnetoresistive tunneling barrier;

a bit magnetic region positioned on one side of the electrically insulating material, the bit magnetic region having a bit magnetic moment that is a polarity in a bit easy axis when there is no applied magnetic field;

a reference magnetic region positioned on an opposite side of the electrically insulating material, the reference magnetic region having an aspect ratio of the reference magnetic region of approximately 1 and comprising a single unpinned ferromagnetic layer of sufficient thickness to form a magnetic vortex with net zero magnetic moment when the applied magnetic field is zero, wherein the electrically insulating material and the bit and reference magnetic regions form a magnetoresistive tunneling junction device (MTJD); and

a means for inducing an applied magnetic field in the bit and reference magnetic regions,

wherein the MTJD has a reference magnetoresistance when the applied magnetic field has a magnitude of zero, and

wherein the polarity of the bit magnetic moment is reliably indicated by a sign of a change of the magnetoresistance of the MTJD from the reference magnetoresistance and the state of the bit magnetic moment is not switched, when the applied magnetic field has a sense value that is within a non-switching magnetic field region and a vortex field region.

27. The magnetoresistive tunneling junction memory cell according to claim 26, wherein the aspect ratio of the reference magnetic region is less than 1.3.

28. The magnetoresistive tunneling junction memory cell according to claim 26, wherein the bit magnetic region comprises N ferromagnetic layers which are anti-ferromagnetically coupled, where N is an integer number greater than or equal to two, and each layer has a thickness.

29. The magnetoresistive tunneling junction memory cell according to claim 28, wherein the N ferromagnetic layers are anti-ferromagnetically coupled by sandwiching a layer of anti-ferromagnetic coupling material between each adjacent pair of ferromagnetic layers.

30. The magnetoresistive tunneling junction memory cell according to claim 26, wherein the means for inducing an applied magnetic field in the bit and reference magnetic regions comprises:

a word line passing near one of the bit and reference magnetic regions; and

a digit line orthogonal to the word line and passing near the other of the bit and reference magnetic regions, and

wherein the word and digit lines are oriented 45 degrees with respect to the bit easy axis.

31. The magnetoresistive tunneling junction memory cell according to claim 30, wherein the means for inducing an applied magnetic field in the bit and reference magnetic regions further comprises a read line passing near the reference magnetic region.

32. The magnetoresistive tunneling junction memory cell according to claim 26, wherein the means for inducing an applied magnetic field in the bit and reference magnetic regions comprises:

a word line passing near one of the bit and reference magnetic regions; and

a digit line orthogonal to the word line and passing near the other of the bit and reference magnetic regions, and

wherein one of the word and digit lines is oriented substantially orthogonally to the bit easy axis.

33. An integrated circuit comprising the magnetoresistive tunneling junction memory cell according to claim 26.

34. An electro-optical equipment comprising the magnetoresistive tunneling junction memory cell according to claim 26.

35. A magnetoresistive tunneling junction memory cell comprising:

an electrically insulating material designed to form a magnetoresistive tunneling barrier;

a bit magnetic region positioned on one side of the electrically insulating material, the bit magnetic region having a bit magnetic moment that has a polarity in a bit easy axis when there is no applied magnetic field;

a reference magnetic region positioned on an opposite side of the electrically insulating material, wherein the electrically insulating material and the bit and reference magnetic regions form a magnetoresistive tunneling junction device (MTJD); and

current carrying conductors for inducing an applied magnetic field in the bit and reference magnetic regions,

wherein the reference magnetic region has a reference magnetic moment that has at least a first and a second value that correspond to first and second values of the applied magnetic field, and

wherein the polarity of the bit magnetic moment is reliably determined by measurements of a magnetoresistance of the MTJD made at the first and second values of the applied magnetic field, and

wherein the first and second values of the applied magnetic field are within a non-switching magnetic field region within which the polarity of the bit magnetic moment is not switched.

36. An integrated circuit comprising the magnetoresistive tunneling junction memory cell according to claim 35.

37. An electro-optical equipment comprising the magnetoresistive tunneling junction memory cell according to claim 35.