Non-volatile memory device with erase address register

• US 6,654,289 B2
• Filed: 10/07/2002
• Issued: 11/25/2003
• Est. Priority Date: 03/09/2001
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): HO, HOAI V
• Application Number:
  US10/265,960
• Publication Number:
  US 20030067805A1
• Time in Patent Office: 414 Days
• Field of Search: 365/185.22, 365/185.11, 365/185.29, 365/185.33, 365/185.01
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A non-volatile memory device includes an array of non-volatile memory cells. The memory has control circuitry to erase the non-volatile memory cells and perform erase verification operations. The memory can be arranged in numerous erasable blocks and/or sub-blocks. An erase register stores data indicating an erase state of corresponding memory sub-blocks. During erase verification, the memory programs the erase register when a non-erased memory cell is located in a corresponding sub-block. Additional erase pulses can be selectively applied to sub-blocks based upon the erase register data. Likewise, erase verification operations can be selectively performed on sub-blocks based upon the erase register data. An address register is provided to store an address of a non-erased memory cell identified during verification. The address from the register is used as a start address for subsequent verification operations on the same array location.

Claims

1. A method for performing an erase verification operation on a non-volatile memory device, the method comprising;

sequentially reading memory cells of a block of memory cells;

identifying a first memory cell that is not erased;

storing an address of the first memory cell in a register circuit;

terminating the sequential reading;

performing an erase operation on the block of memory cells;

retrieving the first address after performing the erase operation;

loading the first address into an address counter circuit; and

sequentially reading the memory cells of the block of memory cells starting at the address of the first memory cell.

2. A flash memory device comprising:

a flash memory array having a plurality of memory cells;

a state machine for controlling memory functions of the flash memory device including performing an erase verification operation that comprises sequentially reading memory cells of a block of memory cells, identifying a first memory cell that is not erased, storing an address of the first memory cell in a register circuit, terminating the sequential reading, performing an erase operation on the block of memory cells, retrieving the first address after performing the erase operation, loading the first address into an address counter circuit, and sequentially reading the memory cells of the block of memory cells starting at the address of the first memory cell.

3. An electronic system comprising:

a processor that generates an erase command; and

a flash memory device coupled to the processor, the flash memory device comprising;

a flash memory array having a plurality of memory cells;

a state machine for controlling memory functions of the flash memory device including performing an erase verification operation, after execution of the erase command, that comprises sequentially reading memory cells of a block of memory cells, identifying a first memory cell that is not erased, storing an address of the first memory cell, terminating the sequential reading, performing an erase operation on the block of memory cells, retrieving the first address after performing the erase operation, loading the first address into an address counter circuit, and sequentially reading the memory cells of the block of memory cells starting at the address of the first memory cell.