Flash memory device
First Claim
1. A flash memory device, comprising:
- a flash memory cell array;
a multiplexer for selecting bit lines of the flash memory cell array;
a decoder for selecting word lines of the flash memory cell array depending on global word line signals, a control signal, local word line signals, and pre-decoding signals;
an internal voltage generator for generating an internal voltage; and
a source control unit for applying the internal voltage from the internal voltage generator to sources of an unselected flash memory cell depending on the global word line signals, a sector program signal, a sector coding signal and a readout signal.
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Abstract
The present invention relates to a flash memory device. The flash memory device comprises a flash memory cell array; a multiplexer for selecting bit lines of said flash memory cell array; a decoder for selecting word lines of said flash memory cell array depending on global word line signals, a control signal, local word line signals and pre-decoding signals; an internal voltage generator for generating a given internal voltage; and a source control unit for applying the internal voltage from said internal voltage generator to sources of a not-selected flash memory cell depending on the global word line signals, a sector program signal, a sector coding signal and a readout signal. Therefore, the present invention can increase the threshold voltage of a not-selected cell and can compensate for reduction in the threshold voltage of the not-selected cell by a drain coupling depending on a drain voltage supplied to bit lines of a selected cell. Thus, the present invention can reduce the chip size and improve the program speed.
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Citations
30 Claims
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1. A flash memory device, comprising:
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a flash memory cell array;
a multiplexer for selecting bit lines of the flash memory cell array;
a decoder for selecting word lines of the flash memory cell array depending on global word line signals, a control signal, local word line signals, and pre-decoding signals;
an internal voltage generator for generating an internal voltage; and
a source control unit for applying the internal voltage from the internal voltage generator to sources of an unselected flash memory cell depending on the global word line signals, a sector program signal, a sector coding signal and a readout signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
first and second switching means for controlling a potential of a first node depending on the global word line signals and the control signal;
an inverting means for inverting the control signal; and
a plurality of decoding circuits for selecting the word lines of the flash memory cell array selected by the local word line signals and the pre-decoding signals depending on the potential of the first node.
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4. The device according to claim 3, wherein the first switching means includes a PMOS transistor driven by the global word line signals.
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5. The device according to claim 3, wherein the second switching means includes a NMOS transistor, driven by the control signal, connected between the first node and a ground terminal.
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6. The device according to claim 3, wherein the plurality of decoding circuits include:
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a first switching means for supplying the local word line signals to the word line depending on the potential of the first node;
a second switching means for controlling a potential of the word lines depending on an output signal of the inverting means; and
a third switching means for controlling the potential of the word lines depending on the pre-decoding signals.
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7. The device according to claim 6, wherein the first switching means includes a PMOS transistor, driven by the potential of the first node, connected between an input terminal of the local word line signals and the word line.
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8. The device according to claim 6, wherein the second switching means includes a triple NMOS transistor, driven by the output signal of the inverting means, connected between the word line and a negative high voltage input terminal.
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9. The device according to claim 6, wherein the third switching means includes a triple NMOS transistor, driven by the pre-decoding signals, connected between the word line and a negative high voltage input terminal.
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10. The device according to claim 1, wherein the source control unit includes a plurality of source control means dependent upon the sector coding signal.
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11. The device according to claim 10, wherein the plurality of source control means include:
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a first logic means for logically combining the sector program signal and the sector coding signal;
a second logic means for logically combining an output signal of the first logic means and the readout signal;
a first switching means for supplying the internal voltage generated in the internal voltage generator to a source of the flash memory cell array depending an output signal of the second logic means;
a second switching means for controlling a potential of a source terminal depending on the global word line signals; and
a third switching means for controlling the potential of the source terminal depending on the readout signal.
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12. The device according to claim 11, wherein the first logic means includes a NAND gate.
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13. The device according to claim 11, wherein the second logic means includes a NOR gate.
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14. The device according to claim 11, wherein the first switching means includes a NMOS transistor connected between the internal voltage generator and the source terminal of the flash memory cell array.
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15. The device according to claim 11, wherein the second switching means includes a NMOS transistor, driven by the global word line signals, connected between the source terminal of the flash memory cell array and a ground terminal.
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16. The device according to claim 11, wherein the third switching means includes a NMOS transistor, driven by the readout signal, connected between the source terminal of the flash memory cell array and a ground terminal.
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17. A flash memory device, comprising:
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a flash memory cell array;
a multiplexer for selecting bit lines of the flash memory cell array;
a decoder for selecting word lines of the flash memory cell array depending on global word line signals, a control signal, local word line signals and pre-decoding signals;
an internal voltage generator for generating an internal voltage; and
a source control unit for applying the internal voltage from the internal voltage generator to sources of an unselected flash memory cell depending on a sector program signal and a potential of the word lines. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
first and second switching means for controlling a potential of a first node dependent upon the global word line signals and the control signal;
an inverting means for inverting the control signal; and
a plurality of decoding circuits for selecting the word lines of the flash memory cell array selected by the local word line signals and the pre-decoding signals depending on the potential of the first node.
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20. The device according to claim 19, wherein the first switching means includes a PMOS transistor that is driven by the global word line signals.
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21. The device according to claim 19, wherein the second switching means includes a NMOS transistor, driven by the control signal, connected between the first node and a ground terminal.
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22. The device according to claim 19, wherein the plurality of decoding circuits include:
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a first switching means for supplying the local word line signals to the word line depending on the potential of the first node;
a second switching means for controlling the potential of the word lines depending on an output signal of the inverting means; and
a third switching means for controlling the potential of the word lines depending on the pre-decoding signals.
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23. The device according to claim 22, wherein the first switching means includes a PMOS transistor, driven by the potential of the first node, connected between an input terminal of the local word line signals and the word line.
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24. The device according to claim 22, wherein the second switching means includes a triple NMOS transistor, driven by the output signal of the inverting means, connected between the word line and a negative high voltage input terminal.
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25. The device according to claim 22, wherein the third switching means includes a triple NMOS transistor, driven by the pre-decoding signals, connected between the word line and a negative high voltage input terminal.
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26. The device according to claim 17, wherein the source control unit includes a plurality of source control means dependent upon the sector coding signal.
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27. The device according to claim 26, wherein the plurality of source control means include:
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a first switching means for supplying the internal voltage from the internal voltage generator to source terminals of the flash memory cell array depending on the sector program signal;
a second switching means for controlling a potential of the source terminals of the flash memory cell array depending on the potential of the word lines; and
a third switching means for controlling the potential of the word lines depending on the potential of the source terminals of the flash memory cell array.
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28. The device according to claim 27, wherein the first switching means includes a NMOS transistor, driven by the sector program signal, connected between the internal voltage generator and the source terminals of the flash memory cell array.
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29. The device according to claim 27, wherein the second switching means includes a NMOS transistor, driven by the potential of the word lines, connected between the source terminals of the flash memory cell array and a ground terminal.
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30. The device according to claim 27, wherein the third switching means includes a NMOS transistor, driven by the source terminal of the flash memory cell array, connected between the word lines and a ground terminal.
Specification