Semiconductor memory device with an adaptive output driver

• US 6,654,310 B2
• Filed: 07/18/2002
• Issued: 11/25/2003
• Est. Priority Date: 09/24/2001
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Nam, Ki-Jun
• Primary Examiner(s): Lebentritt, Michael S.
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US10/197,539
• Publication Number:
  US 20030058732A1
• Time in Patent Office: 495 Days
• Field of Search: 365/230.08, 365/230.06, 365/189.11, 365/210, 365/240, 365/189.08, 365/189.09, 365/189.07, 365/189.05
• US Class Current: 365/230.06
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Abstract

A semiconductor memory device employs an adaptive output driver to vary the strength of the output driver with the variation in external voltage and temperature. For this purpose, the semiconductor memory device with the adaptive output driver includes a shift register unit for producing a control signal so as to control the voltage level of the adaptive output driver, a data masking buffer for generating a reference voltage to be compared with the voltage level of the adaptive output driver, an adaptive output driver for varying its strength in response to the control signal provided from the shift register unit, and a comparator for comparing the reference voltage with the voltage level of the adaptive output driver to thereby generate a signal determining whether or not the shift register unit should perform a shift operation.

Claims

1. A semiconductor memory device with an adaptive output driver, comprising:

a control means for producing a control signal so as to control a voltage level of the adaptive output driver;

data masking buffering means for generating a reference voltage to be compared with the voltage level of the adaptive output driver;

the adaptive output driver whose strength varies in response to the control signal provided from the control means; and

comparison means for comparing the reference voltage with the voltage level of the adaptive output driver to thereby generate a signal determining whether or not the control means should perform a shift operation.

2. The semiconductor memory device as recited in claim 1, wherein the control means includes shift register means for producing the control signal by shifting input signals.

3. The semiconductor memory device as recited in claim 2, wherein the adaptive output driver includes:

a plurality of pull-up transistors for pull-up driving an output terminal of the semiconductor memory device in response to the control signal of the shift register means and a control signal of a pre-driver; and

a plurality of pull-down transistors, connected to the plurality of pull-up transistors in parallel, for pull-down driving the output terminal in response to the control signal of the shift register means and the control signal of the pre-driver.

4. The semiconductor memory device as recited in claim 3, wherein the plurality of pull-up transistors consist of 4 PMOS transistors which are turned-on or turned-off in response to the control signal of the shift register means.

5. The semiconductor memory device as recited in claim 4, wherein among the 4 PMOS transistors, the number of transistors to be turned-off increases depending on the comparison result of the comparison means.

6. The semiconductor memory device as recited in claim 3, wherein the plurality of pull-down transistors consist of 4 NMOS transistors which are turned-on or turned-off in response to the control signal of the shift register means.

7. The semiconductor memory device as recited in claim 6, wherein among the 4 NMOS transistors, the number of transistors to be turned-off increases depending on the comparison result of the comparison means.

8. The semiconductor memory device as recited in claim 3, wherein the shift register means includes:

a pull-up shift register for receiving the signal generated from the comparison means to thereby produce a control signal controlling the plurality of pull-up transistors; and

a pull-down shift register for receiving the signal produced from the comparison means to thereby generate a control signal controlling the plurality of pull-down transistors.

9. The semiconductor memory device as recited in claim 2, wherein the data masking buffering means includes a PMOS transistor group consisting of a plurality of PMOS transistors connected in series and an NMOS transistor group consisting of a multiplicity of NMOS transistors connected in series, wherein the PMOS transistor group and the NMOS transistor group are attached to each other serially, vertically and symmetrically and a node connecting the PMOS transistor group and the NMOS transistor group is attached to a termination voltage Vtt node.

10. The semiconductor memory device as recited in claim 9, wherein the PMOS transistor group and the NMOS transistor group contain 3 PMOS transistors and 3 NMOS transistors, respectively.

11. The semiconductor memory device as recited in claim 9, wherein among the PMOS transistor group, a resistor is connected between a gate and a drain of some PMOS transistors and among the NMOS transistor group, a resistor is attached between a gate and a drain of some NMOS transistors.