Joint maximum likelihood frame and timing estimation for a digital receiver

• US 6,654,432 B1
• Filed: 06/08/1998
• Issued: 11/25/2003
• Est. Priority Date: 06/08/1998
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Wireless Facilities Incorporated (Kratos Defense & Security Solutions Incorporated)
• Inventors: Safavi, Saeid, Lakkis, Ismail, Tayebi, Masood K., OʼShea, Deirdre
• Primary Examiner(s): Pham, Chi
• Assistant Examiner(s): BURD, KEVIN MICHAEL
• Application Number:
  US09/093,414
• Time in Patent Office: 1,996 Days
• Field of Search: 375/326, 375/324, 375/340, 375/136, 375/355, 375/369, 375/365, 375/373, 375/376, 375/346, 375/344, 375/348, 375/371, 375/354
• US Class Current: 375/354
• CPC Class Codes: H04L 7/0029 interpolation of received data signal
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15
• CPC Class Codes: H04W 84/14 WLL [Wireless Local Loop]; RLL [Radio Local Loop]

Abstract

A receiver for receiving a signal stream in a digital radio communication system. The signal stream includes data frames where each frame including a data signal sequence and a synchronizing signal sequence. The communication system synchronizes the receiver by employing the signal stream. The receiver includes a sampling circuit for sampling symbol levels in the synchronizing signal sequence and a synchronization subsystem. The synchronization subsystem utilizes a frame synchronization circuit, a dynamic interpolator and a decision-directed phase tracking mechanism for removing residual frequency and phase offsets. The synchronization subsystem also includes a threshold detection mechanism for comparing values derived from the sampled frame synchronization output with a predefined value which determines whether synchronization has occurred or not. The dynamic interpolator includes a circuit for generating the interpolation coefficients for timing and initial phase estimation, a maximum likelihood timing and phase estimator, and a data interpolation and decimation unit. The estimated timing offset and phase offset in the dynamic interpolator may change for each frame in the signal stream.

Claims

1. A synchronization circuit, comprising:

a frame synchronizer receiving a data stream that includes data frames;

a dynamic interpolation module receiving a phase corrected version of the data stream, generating an estimated timing offset, and correcting the phase corrected version of the data stream with the generated timing offset to generate a timing and phase corrected data stream, wherein the dynamic interpolation module includes a timing estimator that utilizes the output of the frame synchronizer to estimate a timing offset, and wherein the estimated timing offset may change for each frame of the data stream; and

a module for removing a residual phase offset from the timing and phase corrected data stream.

2. A method of synchronizing a digital communications receiver, comprising:

receiving a signal stream comprising a plurality of data frames;

obtaining a frame synchronization signal from the signal stream;

dynamically interpolating a phase offset and a timing offset of the signal stream from the frame synchronization signal;

correcting the received signal stream with the dynamically interpolated phase offset and timing offset to generate a timing and phase corrected data stream; and

removing a residual phase offset from the timing corrected and phase corrected data stream.

3. A method of receiving a signal stream in a digital communications receiver, comprising:

providing an analog signal stream;

convening the analog signal stream to a digital signal stream;

correlating a unique word wit the digital signal stream;

detecting a threshold to determine whether frame synchronization has occurred;

generating coefficients for timing estimation and phase estimation in response to detecting the threshold;

estimating a timing offset and a phase offset for the digital signal stream;

generating a timing corrected and initial phase corrected signal stream from the estimated timing offset, estimated phase offset and the digital signal stream; and

removing residual phase offsets from the tinting corrected and initial phase corrected signal stream.

4. The method defined in claim 3, wherein the converting is at a rate of two samples per symbol.

5. The method defined in claim 3, wherein the estimating the timing offset and the phase offset utilizes a predetermined maximum likelihood technique.

6. A digital system for detecting data, comprising:

a frame synchronizer receiving a data stream;

a timing and phase estimator that utilizes the output of the frame synchronizer to estimate a timing offset and a phase offset;

a phase rotation module receiving the estimated phase offset and the data stream to perform an initial phase correction on the data stream using the estimated phase offset;

an interpolation module receiving the estimated timing offset and the phase corrected data stream to generate a timing corrected data stream; and

a phase tracking and data detection module receiving the timing corrected data stream to remove a residual phase offset and detect the data.

7. The system defined in claim 6, wherein the data stream received by the frame synchronizer is sampled at a rate of two samples per symbol.

8. The system defined in claim 6, wherein the timing and phase estimator operates using a maximum likelihood process.

9. The system defined in claim 6, wherein the timing and phase estimator may estimate a different timing offset and a different phase offset for each frame of the data stream.

10. The system defined in claim 6, wherein the interpolation module is dynamic and operates on a different estimated timing offset for each frame of the data stream.

11. The system defined in claim 6, wherein the interpolation module includes a decimator to decimate the timing corrected data stream.

12. The system defined in claim 6, wherein the phase tracking and data detection module is a feedforward circuit.

13. The system defined in claim 6, additionally comprising a frame detector receiving the results of the frame synchronizer and providing a frame synchronization detection instant to the timing and phase estimator.

14. The system defined in claim 13, wherein the frame synchronization detection instant is representative of a maximum of the frame synchronization output.

15. The system defined in claim 13, additionally comprising an interpolation coefficient module receiving the results from the frame synchronizer and the frame detector and providing at least one interpolation coefficient to the timing and phase estimator.

16. The system defined in claim 15, wherein the interpolation coefficients are used by the timing and phase estimator to estimate the timing offset.

17. A synchronization circuit in a digital wireless receiver, comprising:

a frame synchronizer receiving a data stream;

a timing and phase estimator that utilizes the output of the frame synchronizer to estimate a timing offset and a phase offset;

a derotator receiving the estimated phase offset and the data stream to perform an initial phase correction on the data stream using the estimated phase offset;

an interpolation module receiving the estimated timing offset and the phase corrected data stream to generate a interpolated data stream; and

a phase tracking and data detection module receiving the interpolated data stream to remove a residual phase offset and synchronize the data in the data stream.

18. A digital communications receiver capable of receiving a signal stream having a plurality of data frames, wherein the signal stream is used to synchronize portions of the receiver, comprising:

a sampling circuit capable of sampling symbol levels in a synchronizing signal sequence of a data frame;

a pulse shaping filter capable of receiving and filtering the sampled signal sequence;

a frame synchronization circuit capable of receiving the filtered signal sequence and correlating a unique word with the filtered signal sequence;

a threshold detection mechanism in communication with the frame synchronization circuit and capable of determining whether synchronization has occurred;

an interpolation coefficient module in communication with the frame synchronization circuit and capable of generating coefficients for timing estimation and phase estimation;

a timing and phase estimator that utilizes the output of the frame synchronization circuit and of the interpolation coefficient module to estimate a timing offset and a phase offset;

an interpolation module receiving the estimated timing offset and the signal stream to generate a timing corrected signal stream; and

a decision directed phase tracker capable of receiving the timing corrected signal stream and removing residual phase offsets.

19. The system defined in claim 18, wherein the estimated timing offset may change for each frame of the data stream.

20. The system defined in claim 18, wherein a one of the data frames comprises a data signal sequence and a synchronizing signal sequence.

21. The system defined in claim 18, wherein the threshold detection mechanism compares values derived from the frame synchronization circuit with a predefined value.