MPEG video decoding system and overflow processing method thereof

• US 6,654,500 B1
• Filed: 12/28/1998
• Issued: 11/25/2003
• Est. Priority Date: 12/29/1997
• Status: Expired due to Term

• Current Assignee: LG Electronics, Inc. (LG Corporation)
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Lyu, Hwa Young
• Primary Examiner(s): Johns, Andrew W.
• Assistant Examiner(s): Alavi, Amir
• Application Number:
  US09/221,823
• Time in Patent Office: 1,793 Days
• Field of Search: 382/232, 382/233, 382/234, 382/236, 382/237, 382/238, 382/239, 382/240, 382/241, 382/242, 382/243, 348/384, 348/423.1, 348/419.1, 348/425.2, 375/240.01, 375/240.27, 375/240.26, 375/240.28, 375/240.29, 375/240.25
• US Class Current: 382/233
• CPC Class Codes: H04N 19/152 by measuring the fullness of the transmission buffer
• CPC Class Codes: H04N 19/50 using predictive coding H04N19/61 takes precedence
• CPC Class Codes: H04N 19/89 involving methods or arrangements for detection of transmission errors at the decoder
• CPC Class Codes: H04N 19/895 in combination with error concealment
• CPC Class Codes: H04N 19/90 using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
• CPC Class Codes: H04N 21/4341 Demultiplexing of audio and video streams
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer
• CPC Class Codes: H04N 21/4425 Monitoring of client processing errors or hardware failure

Abstract

An MPEG video decoding system and an overflow processing method are disclosed. The MPEG video decoding system does not reset the video buffer during the overflow period, which allows a decoding of the data already stored in the video buffer, thereby minimizing the loss of data due to an overflow.

Claims

1. An MPEG video decoding system, comprising:

a video buffer coupled to store a received video bit stream and configured to output a control signal, the control signal indicating overflow if an overflow condition occurs in the video buffer and otherwise indicating non-overflow; and

a DEMUX coupled to output the video bit stream to the video buffer and receive the control signal from the video buffer, said DEMUX configured to discard the video bit stream if the control signal indicates overflow and to output the video bit stream to the video buffer if the control signal indicates non-overflow, wherein if the control signal indicating non-overflow is received subsequent to the control signal indicating overflow, upon resuming outputting of the video bitstream, the DEMUX inserts an error code into the video bit streams upon resuming outputting the video bit streams to the video buffer.

2. The system of claim 1, wherein the video buffer is not reset if an overflow occurs.

3. The system of claim 1, wherein the error code is a sequence error code.

4. The system of claim 1, further comprising a video decoder coupled to receive and decode the video bit streams stored in the video buffer, wherein the video decoder skips decoding of the video bit streams if the error code is detected from the stored video bit stream.

5. The system of claim 4, wherein the DEMUX inserts a code indicating a normal decoding after the insertion of the error code.

6. The system of claim 5, wherein the video decoder continues decoding of the video bit streams when the code indicating a normal decoding is detected from the stored video bit stream.

7. The system of claim 5, wherein the code indicating a normal decoding comprises an initial code.

8. The system of claim 1, wherein the error code is inserted into the video bit streams after recovering from an overflow condition to indicate a discontinuity in the video bit streams.

9. The system of claim 1, further comprising a video decoder coupled to receive and decode the video bit streams stored in the video buffer, wherein the video decoder skips the decoding of the video bit streams if an overflow condition is detected.

10. The system of claim 9, wherein the video decoder skips decoding when the video buffer resumes outputting of the video bit stream, including the inserted error code, after the overflow condition is corrected, and wherein the video decoder resumes decoding when an initialization code is received in the video bitstream subsequent to the error code.

11. An MPEG video decoding system comprising:

a video buffer configured to store video bit streams, said video buffer outputting a control signal indicating overflow if an overflow occurs and otherwise indicating non-overflow;

a DEMUX coupled to receive and demultiplex an input video bit stream and coupled to receive the control signal, wherein said DEMUX discards the video bit streams if the control signal indicates overflow and outputs the video bit streams to the video buffer if the control signal indicates non-overflow; and

a video decoder coupled to receive an output of the video buffer and decode the received video bit streams, and wherein the video buffer is not reset if an overflow occurs, wherein the DEMUX inserts an error code into the video bit streams prior to outputting the video bit streams to the video buffer when the signal indicating non-overflow is received from the video buffer subsequent to receiving the signal indicating an overflow, and wherein the DEMUX inserts a code indicating a normal decoding after the insertion of the error code.

12. The system of claim 11, wherein the video decoder skips decoding of the video bit streams if the error code is detected from the stored video bit streams and wherein the video decoder resumes decoding of the video bit streams when the code indicating a normal decoding is detected from the stored video bit stream.

13. The system of claim 12, wherein the error code is a sequence error code.

14. The system of claim 13, wherein the code indicating a normal decoding is an initial code.

15. The method of claim 14, further comprising one of decoding the video bit streams stored in the video buffer and the skipping the decoding of the video bit streams stored in the video buffer, wherein the decoding is skipped when the control signal indicates overflow.

16. The system of claim 11, wherein the error code is inserted into the video bit streams after recovering from an overflow condition to indicate a discontinuity in the video bit streams.

17. The system of claim 11, further comprising a video decoder coupled to receive and decode the video bit streams stored in the video buffer, wherein the video decoder skips the decoding of the video bit streams if an overflow condition is detected.

18. An overflow processing method of an MPEG video decoding system, comprising:

storing video bit streams in a video buffer for decoding, and generating a control signal to indicate overflow if an overflow occurs and otherwise to indicate non-overflow;

receiving the control signal in a demultiplexer; and

receiving and demultiplexing an input video bit stream in the demultiplexer and one of discarding the video bit stream and outputting the video bit stream to the video buffer, wherein the video bit stream is discarded if the control signal indicates overflow, and wherein the video bit stream is outputted to the video buffer if the control signal indicates non-overflow, wherein demultiplexing the video bit streams further comprises inserting an error code into the video bit streams upon resuming outputting the video bit streams to the video buffer when the signal indicating non-overflow is received from the video buffer subsequent to the signal indicating overflow.

19. The method of claim 18, wherein the error code is a sequence error code.

20. The method of claim 18, further comprising:

decoding the video bit streams stored in the video buffer;

detecting whether the error code has been inserted into the video bit streams; and

skipping decoding of the video bit streams if the error code is detected from the stored video bit stream.

21. The method of claim 20, further comprising inserting a code indicating a normal decoding into the demultiplexed bit stream subsequent to the insertion of the error code.

22. The method of claim 21, wherein the decoding step further comprises:

detecting the code indicating a normal decoding; and

continuing decoding of the video bit streams when the code indicating a normal decoding is detected from the stored video bit stream.

23. The method of claim 22, wherein the code indicating a normal decoding is an initial code.

24. The method of claim 18, wherein the error code is inserted into the video bit streams after recovering from an overflow condition to indicate a discontinuity in the video bit streams.

25. An MPEG video decoding system, comprising:

an input circuit, coupled to receive a data stream and a control signal, and configured to output or discard a video bit stream according to the control signal; and

a buffer, coupled to receive the video bit stream from the input circuit and output the video bit stream at a constant rate; and

a decoder coupled to receive the video bit stream from the buffer, wherein the decoder stops decoding the video bit stream if the error code is detected in the video bit stream, and resumes decoding when a normal status code is detected in the video bit stream, wherein the buffer generates the control signal indicating an available or unavailable state of the buffer and provides the control signal to the input circuit, and wherein the input circuit discards the video bit stream output when the buffer is in the unavailable state, and wherein the input circuit inserts an error code into the video bit stream when the control signal is returned to the available state after being in the unavailable state and resumes outputting the video bitstream including the error code.

26. The system of claim 25, wherein the input circuit comprises a demultiplexer.

27. The system of claim 25, wherein the buffer comprises a video buffer.

28. The system of claim 25, further comprising a video decoder coupled receive to the video bit stream at the constant rate from the buffer.

29. The system of claim 28, wherein the video decoder skips decoding when the video buffer resumes outputting of the video bit stream, including the inserted error code, after the non-available condition is corrected, and wherein the video decoder resumes decoding when an initialization code is received in the video bitstream subsequent to the error code.

30. The system of claim 25, wherein the error code indicates a discontinuity in the video bit stream.

31. The system of claim 30, wherein the input circuit inserts the normal status code into the bit stream after insertion of the error code.

32. The system of claim 31 wherein the normal status is detected when the video decoder receives an initialization code in the video bit stream after receiving the error code in the video bit stream.

33. The system of claim 25, wherein the buffer maintains its data without resetting if the unavailable state occurs.

34. The system of claim 25, wherein the unavailable state indicates an overflow condition of the buffer.

35. The system of claim 25, wherein the unavailable state occurs when the buffer is filled to capacity, but before a data overflow.