Digitized automatic gain control system and methods for a controlled gain receiver

• US 6,654,594 B1
• Filed: 05/30/2000
• Issued: 11/25/2003
• Est. Priority Date: 05/30/2000
• Status: Expired due to Fees

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Oakley, John Richard, Powell, Clinton C II, Hughes, James David
• Primary Examiner(s): Nguyen, Lee
• Assistant Examiner(s): TRAN, TUAN A
• Application Number:
  US09/580,770
• Time in Patent Office: 1,274 Days
• Field of Search: 455/232.1, 455/234.1, 455/234.2, 455/240.1, 455/242.2, 455/245.1, 375/345, 375/316-317
• US Class Current: 455/245.1
• CPC Class Codes: H03G 3/001 Digital control of analog signals
• CPC Class Codes: H03G 3/3089 Control of digital or coded signals
• CPC Class Codes: H04B 17/318 Received signal strength
• CPC Class Codes: H04W 52/52 using AGC [Automatic Gain Control] circuits or amplifiers

Abstract

An automatic gain control (AGC) system (100) for a controlled gain receiver (1101) includes a magnitude generator (160) and a gain corrector (170). The magnitude generator (160) generates a binary voltage squared signal (165) having a binary value that is directly proportional to a recovered signal power of an intercepted signal (113). The gain corrector (170) determines an adjustment of a gain control value (195) as a multiple of increments that are approximately 3 decibel (dB), by shifting (475, 445) a reference threshold by one or more bits and comparing (485, 455) the shifted reference threshold to the binary voltage squared signal. An initial setting of a state of a step attenuator (114) during a track mode (172) is determined during a warm up mode (171) by comparing the binary voltage squared signal (165) to two different thresholds (245, 255).

Claims

1. An automatic gain control (AGC) system for a receiver, comprising:

a magnitude generator that generates a binary voltage squared signal having a binary value that is directly proportional to a recovered signal power of an intercepted signal; and

a gain corrector that determines a gain control value adjustment as a multiple of increments that are approximately 3 decibel (dB), by shifting a first value by one or more bits and comparing the shifted first value to a second value, wherein each of the first and second values are one of the binary voltage squared signal and a predetermined threshold.

2. The AGC system of claim 1, wherein the binary voltage squared signal is generated from a digital I squared signal plus a digital Q squared signal recovered from the intercepted signal.

3. The AGC system of claim 1, wherein the multiple is determined by first determining a sign of a difference of the first value and the second value, and shifting the first value in a direction determined by the sign until the sign of the difference changes.

4. he AGC system of claim 1, wherein a new gain control value is determined from the gain control value adjustment and a previously stored gain.

5. The AGC system of claim 1, wherein the new gain control value is limited by stored minimum and maximum gain limits.

6. The AGC system of claim 1, wherein the gain adjustment is further limited by a maximum gain adjustment amount.

7. The AGC system of claim 1, further comprising:

a low noise amplifier (LNA) having an analog input and a gain,

wherein the gain corrector uses the gain control value adjustment to determine a new gain control value that is a binary word, and further wherein the gain corrector compensates for delays in the AGC system and latches the new gain control value into a digital to analog converter (DAC) coupled to the analog input such that the gain of the LNA is changed essentially at a symbol edge time within the LNA.

8. The AGC system of claim 7, wherein the gain corrector latches the new gain control value only when the new gain control value is sufficiently different from a previous gain control value.

9. The AGC system of claim 7, further comprising an AGC filter coupled to the gain corrector, wherein, in response to the new gain control value being latched, the AGC filter is cleared and kept reset for a predetermined number of clock periods.

10. The AGC system of claim 9, wherein the AGC filter comprises:

an integrator that generates an integrator output signal having a magnitude from an input signal coupled thereto, wherein the integrator is also coupled to a bandwidth signal that controls a bandwidth of the AGC filter; and

a scalar coupled to the integrator output signal and the bandwidth signal, that generates a filter output by scaling the magnitude of the integrator output signal to be independent of the bandwidth.

11. The AGC system of claim 10,

wherein the AGC filter operates in gain control value update cycles,

wherein the input signal comprises a series of digital samples,

wherein the integrator comprises an accumulator that, in response to a symbol rate signal that indicates one of at least two symbol rates that have a factor of two relationship with each other, generates the filter output as a binary signal that is an accumulation of a quantity of the samples occurring during one gain control value update cycle, wherein the ratio of the quantities for any two symbol rates is essentially inversely proportional to the ratio of the two symbol rates;

and

wherein the scalar performs a reduction of the binary output by a factor that is essentially equal to the quantity, by a binary right shift operation.

12. The AGC system of claim 11, wherein the quantity is given by ((2^N)−

1)*2^M, wherein N and M are integers and the binary right shift operation shifts right M+N bits.

13. The AGC system of claim 11, wherein the factor is 2^N *2^M.

14. The AGC system of claim 10, wherein the scaler performs an adjustment of the reduced binary output of ((2^N)+1)/(2^N).

15. The AGC system of claim 9, wherein the AGC filter generates a binary voltage squared signal that has a high resolution bit width, W, and has a binary value, MAG, that is directly proportional to a recovered signal power of an intercepted signal, and, the AGC system further comprising:

a received signal strength indicator (RSSI) function that generates an RSSI output that is a high resolution, uncorrected, filtered signal of bit width W, directly from the binary voltage squared signal when the AGC system is in a suspend test mode.

16. The AGC system of claim 15, further comprising:

a step attenuator coupled to the intercepted signal that attenuates the intercepted signal as determined by an attenuator control signal,

wherein the RSSI function generates an RSSI output that is a low resolution corrected signal of bit width X that has a value essentially equivalent to the power of an intercepted signal determined by a summation of the relative gain of the LNA, a relative attenuation of the step attenuator, an approximate logarithm to the base of 2 of the MAG, and a constant, and wherein X is an integer less than W.

17. The AGC system of claim 1 further comprising:

a step attenuator coupled to the gain corrector for-receiving the intercepted signal, wherein the intercepted signal is transmitted as part of a signaling protocol that includes a plurality of signal cycles, each of which comprises a preamble portion followed by a normal data portion,

wherein the gain corrector further generates an attenuator control signal for setting the step attenuator to one of an attenuate state and a pass through state at the commencement of the normal data portion.

18. The AGC system of claim 17, wherein the gain corrector sets the step attenuator to an attenuate state when, during the preamble portion, the step attenuator is attenuated, a gain control value is at a minimum gain control value, and the signal power of a recovered signal is greater than a predetermined AGC threshold.

19. The AGC system of claim 17, wherein the gain corrector sets the step attenuator to a pass-through state during the normal data portion of the intercepted signal when the recovered signal falls below a predetermined step-out threshold.

20. The AGC system of claim 17, wherein when the gain corrector sets the attenuator control signal to the pass-through state during the normal data portion of the transmission signal, the gain corrector does not set the attenuator control signal to the attenuate state again during the normal data portion of the same transmission signal.