DMA access authorization for 64-bit I/O adapters on PCI bus

• US 6,654,818 B1
• Filed: 06/22/2000
• Issued: 11/25/2003
• Est. Priority Date: 06/22/2000
• Status: Expired due to Fees

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Thurber, Steven Mark
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): PATEL, NIKETA I
• Application Number:
  US09/599,179
• Time in Patent Office: 1,251 Days
• Field of Search: 710/3, 710/23, 710/26, 710/28, 710/305, 710/308, 710/314, 711/202, 711/210
• US Class Current: 710/3
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/404 with address mapping

Abstract

A method, data processing system, and I/O subsystem suitable for authorizing DMA accesses requested by a 64-bit I/O adapter are disclosed. The system includes one or more processors that have access to a system memory. A host bridge is connected between the processor(s) and an I/O bus. A first I/O adapter, which generates 32-bit addresses, is coupled to the host bridge. A second I/O adapter coupled to the host bridge is enabled to generate an address with a width greater than 32-bits (such as a 64-bit address). The system may include a Translation Control Entry (TCE) table, that is configured with information needed to translate an address generated by the 32-bit adapter to a wider address (such as a 64-bit address). In addition, the TCE may determine whether DMA access to the translated address by the requesting adapter is authorized. The system further includes an Access Control Table (ACT). The ACT determines whether DMA access to the address generated by the 64-bit I/O adapter is authorized. The ACT may be formatted as a set of ACT entries where each ACT entry corresponds to a unique portion of the system'"'"'s memory address space. In one embodiment, each ACT entry consists of a single bit that indicates access to a 256 MB or larger portion of the system memory address space. In one embodiment, the I/O bus is a PCI bus. The first and second I/O adapters may be connected to a secondary PCI bus that communicates with the primary PCI bus via a PCI-to-PCI bridge. In one embodiment, each 64-bit I/O adapter has its own ACT table and portions of the ACT table may reside in the PCI-to-PCI bridge.

Claims

1. A data processing system, comprising:

a processor;

a system memory accessible to the processor;

a host bridge connected between the processor and an I/O bus;

a first I/O adapter coupled to the host bridge, wherein the first I/O adapter is enabled to generate a 32-bit address;

a second I/O adapter coupled to the host bridge, wherein the second I/O adapter is enabled to generate a 64-bit address;

a Translation Control Entry (TCE) table suitable for translating an address generated by the first adapter to a 64-bit address and for determining whether DMA access to the translated address is authorized; and

an Access Control Table (ACT), distinct from the TCE and suitable for determining whether DMA access to the address generated by the second I/O adapter is authorized; and

means for processing memory accesses generated by the first adapter through the TCE table and for processing memory accesses generated by the second adapter through the ACT wherein memory accesses generated by the second adapter avoid the TCE.

2. The system of claim 1, wherein the ACT includes a set of ACT entries wherein each ACT entry corresponds to a unique portion of the system'"'"'s memory address space.

3. The system of claim 2, wherein each entry in the ACT includes a single bit indicative of whether an access to the corresponding system memory address space is authorized.

4. The system of claim 2, wherein the size of each unique portion of the memory address space to which each ACT entry corresponds is greater than the size of a portion of memory address space to which each TCE corresponds by a factor of at least 64 K (2¹⁶).

5. The system of claim 4, wherein the system is characterized as a Logically Partitioned (LPAR) system wherein the system memory address space is logically assigned in 256 MB, and further wherein each unique portion of memory comprises 256 MB of address space.

6. The system of claim 1, wherein the I/O bus is characterized as a primary PCI bus and wherein the first and second I/O adapters are connected to a secondary PCI bus that is connected to the primary PCI bus via a PCI-to-PCI bridge.

7. The system of claim 6, wherein at least a portion of the ACT is resident in the PCI-to-PCI bridge.

8. The system of claim 1, further comprising a second 64-bit I/O adapter and a corresponding second ACT, wherein each 64-bit I/O adapter'"'"'s access authorization is determined by its corresponding ACT.

9. In a data processing system, a memory access authorization method, comprising:

responsive to detecting a memory access generated by a 32-bit I/O adapter, translating the 32-bit address to a 64-bit address and authorizing the 32-bit I/O adapter access based upon an entry in a translation control entry (TCE) table;

responsive to detecting a memory access generated by a first 64-bit I/O adapter;

determining the value of an entry in a first Access Control Table (ACT), wherein the entry corresponds to a portion of the system address space that includes the address of the memory access; and

authorizing the 64-bit I/O adapter to access system memory at the memory access address if the determined value of the ACT entry is equal to a predetermined value, wherein memory accesses from the 64-bit adapter are authorized while avoiding the address translation mechanism of the TCE.

10. The method of claim 9, further comprising, responsive to detecting a second memory access generated by a second 64-entry I/O adapter, determining a portion of the system address space corresponding to the address of the second access, determining the value of a entry in a second ACT, and authorizing the second 64-entry I/O adapter to access system memory at the second generated address if the determined value of the entry in the second ACT is equal to a predetermined value.

11. The method of claim 9, wherein the ACT entry consists of a single bit indicative of whether access to the corresponding portion of system memory by the 64-bit adapter is permitted.

12. The method of claim 9, wherein each entry in the ACT corresponds to a unique portion of the system memory address space and further wherein the size of each unique portion is equal.

13. The method of claim 12, wherein the size of each unique portion of address space is at least 256 MB.

14. The method of claim 9, wherein each entry in the ACT corresponds to a portion of the system memory address space that is at least 64K larger than a portion of system memory address to which each TCE corresponds, wherein the number of entries in the ACT table is substantially smaller than the number of TCE'"'"'s.

15. An I/O subsystem of a data processing system that includes processor and system memory, the subsystem comprising:

a host bridge connected between a system bus and a primary PCI bus, wherein the host bridge is enabled to retrieve portions of a Translation Control Entry (TCE) table from system memory responsive to receiving a memory access address from a 32-bit I/O adapter; and

a PCI-to-PCI bridge connected to the host PCI bridge, wherein the PCI-to-PCI bridge is enabled to retrieve portions of a first Access Control Table (ACT) from system memory responsive to receiving a memory access address from a first 64-bit I/O adapter and further enabled to determine whether the first 64-bit I/O adapter is authorized to access the received address wherein memory accesses from the 64-bit adapter are authorized while avoiding the translation mechanism of the TCE.

16. The I/O subsystem of claim 15, wherein the PCI-to-PCI bridge is further enabled to retrieve portions of a second ACT from system memory responsive to receiving a memory access address from a second 64-bit I/O adapter and further enabled to determine whether the second 64-bit I/O adapter is authorized to access the received address.

17. The I/O subsystem of claim 15, wherein the retrieved portion of the first ACT includes an entry that corresponds to a portion of system memory address space that includes the received 64-bit address.

18. The I/O subsystem of claim 17, wherein each entry in the first ACT consists of a single bit indicative of whether accesses to the corresponding portion of system memory are permitted.

19. The I/O subsystem of claim 18, wherein each entry in the first ACT corresponds to 256 MB of system memory address space and each TCE corresponds to 4 KB of memory space wherein the number of ACT entries is less than the number of TCE'"'"'s by a factor of 2¹⁶.

20. The I/O subsystem of claim 15, further comprising:

a second host bridge, additional PCI-to-PCI bridges connected to the second host bridge, and additional I/O adapters connected to the additional PCI-to-PCI bridges, the additional I/O adapters including additional 32-bit and additional 64-bit I/O adapters;

wherein the second host bridge is enabled to retrieve portions of a second TCE table from system memory responsive to receiving a DMA address from one of the additional 32-bit I/O adapters and further enabled to generate a translated address from the received DMA address using the retrieved portion of the second TCE, wherein the width of the translated address exceeds 32 bits.