Method and apparatus for data transfer employing closed loop of memory nodes

• US 6,654,834 B1
• Filed: 07/13/2000
• Issued: 11/25/2003
• Est. Priority Date: 07/16/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bhandal, Amarjit S., Robertson, Iain, Balmer, Keith, Keay, John
• Primary Examiner(s): Myers, Paul R.
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US09/615,645
• Time in Patent Office: 1,230 Days
• Field of Search: 710/107, 710/110, 710/111, 710/113, 710/118, 710/312, 710/241, 710/31, 710/32, 710/33, 710/37-38, 710/60-61, 710/220, 710/240, 710/243, 709/208, 709/209, 709/211, 709/217, 709/238, 709/242, 709/216, 711/149, 711/150, 711/154, 711/169, 370/476, 370/477, 370/492
• US Class Current: 710/107
• CPC Class Codes: G06F 15/173 using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake

Abstract

Data transfer between a master node (300) and plural memory nodes (301-308) follows a synchronous fixed latency loop bus (255). Each memory node includes bus interface (311-318) which passes command, write data, address and read data to a next memory node in the loop. Each memory node performs a read from its memory at the specified address if a read command is directed to it. Each memory node performs a write to its memory at the specified address if a write command is directed to it. This configuration provides a fixed latency between the issue of a read command and the return of the read data no matter which memory node is accessed. This configuration prevents collision of returning read data. This configuration retains the issued read and write order preserving proper function for read/write and write/read command pairs. This configuration provides fixed loading to each stage regardless of the number of memory nodes. Thus the design of large systems operating at high speeds is simplified.

Claims

1. A method of data transfer among a plurality of nodes comprising the steps of:

initializing transfer operations from a master node, said initializing including generating a read command including an indication of one of the plurality of nodes and a memory address;

disposing the plurality of nodes in closed loop having a first node and a last node;

passing a received read command including said indication of one of the plurality of nodes and said memory address from each node to a next node in said closed loop, the first node of the plurality of nodes receiving said read command generated by the master node; and

determining at each node whether a read command including said indication of one of the plurality of nodes and said memory address received from a prior node includes an indication of one of the plurality of nodes corresponding to that node, if so reading data from a memory at an address corresponding to said memory address of said read command and passing said read data to said next node in said closed loop, the last node of said plurality of nodes passing said read data to the master node.

2. The method of claim 1, wherein:

said step of generating a read command including an indication of one of the plurality of nodes generates a node number;

said method further includes assigning a unique node number to each of said plurality of nodes; and

said step of determining whether a read command includes an indication of one of the plurality of nodes corresponding to that node includes determining if said node number of said read command corresponds to said node number assigned to that node.

3. The method of claim 1, wherein:

said step of generating a read command including an indication of one of the plurality of nodes generates a memory address within a unified address space;

said method further includes assigning a unique subset of said unified address space to each of said plurality of nodes; and

said step of determining whether a read command includes an indication of one of the plurality of nodes corresponding to that node includes determining if said memory address of said read command corresponds to said unique subset of said unified address space assigned to that node.

4. The method of claim 1, further comprising:

said step of initializing transfer operations from said master node includes supplying to said first node constant read data along with said read command.

5. The method of claim 1, wherein:

discarding at said last node said read command including said indication of one of said plurality of nodes and said memory address following determining at said last node whether said read command includes an indication of one of the plurality of nodes corresponding to the last node and if so reading data from a memory at an address corresponding to said memory address of said read command and passing said read data to said master node.

6. The method of claim 1 further comprising the steps of:

said step of initializing transfer operations from the master node further includes generating a write command including an indication of one of the plurality of nodes, write data and a memory address; and

determining at each node whether a write command including said indication of one of the plurality of nodes, said write data and said memory address received from a prior node includes an indication of one of the plurality of nodes corresponding to that node, if so writing the write data of said write command to a memory at an address corresponding to said memory address of said write command and passing said write command to said next node in said closed loop.

7. The method of claim 3, wherein:

said step of assigning a unique subset of said unified address space to each of said plurality of nodes includes assigning a unique coding of a predetermined number of most significant bits of said memory address; and

said step of determining whether a read command includes an indication of one of the plurality of nodes corresponding to that node includes determining if said predetermined number of most significant bits of said memory address of said read command corresponds to said unique coding assigned to that node.

8. The method of claim 3, wherein:

said step of assigning a unique subset of said unified address space to each of said plurality of nodes includes assigning a unique address range of said memory address; and

said step of determining whether a read command includes an indication of one of the plurality of nodes corresponding to that node includes determining if memory address of said read command is included within said unique address range assigned to that node.

9. The method of claim 4, wherein:

said step of supplying said first node constant read data supplies read data consisting of all 1'"'"'s.

10. The method of claim 4, wherein:

said step of supplying said first node constant read data supplies read data consisting of all 0'"'"'s.

11. The method of claim 6, further comprising:

discarding at said last node said write command including said indication of one of said plurality of nodes, said write data and said memory address following determining at said last node whether said write command includes an indication of one of the plurality of nodes corresponding to the last node and if so writing the write data of said write command to a memory at an address corresponding to said memory address of said write command.

12. A data processing apparatus comprising:

a plurality of memory nodes disposed in a closed loop having a first memory node and a last memory node;

a master node capable of initializing data transfer operations by generation of a read command including a memory address;

each of said plurality of memory nodes having

a memory having an address input and a data output, said memory outputting data stored therein at addressed memory locations corresponding to an address received at said address input,

a command input for receiving a read command from a prior memory node in said closed loop, said first memory node receiving said read command generated by said master node;

a command output for supplying received read command to a next memory node in said closed loop, said command output of said last memory node not connected,

a read data input for receiving read data from a prior memory node in said closed loop,

a read data output for supplying read data to a next memory node in said closed loop, said last memory node supplying read data to said master node,

an address comparator generating a match signal upon detection that a received read command includes an address corresponding to a unique address range assigned to said memory node,

a multiplexor having a first input connected to said read data input, a second input connected to said data output of said memory and an output connected to said read data output, said multiplexor selectively connecting either said first input or said second input to said output, and

a command decoder connected to said memory, said address comparator, and said multiplexor, said command decoder supplying said received address to said address input of said memory and controlling said multiplexor to connect said second input to said output responsive to a received read command upon receipt of said match signal.

13. The data processing apparatus of claim 12, wherein:

said address comparator detects whether said read command includes a memory address having a predetermined number of most significant bits corresponding to a unique coding assigned to that memory node.

14. The data processing apparatus of claim 12, wherein:

each of said plurality of memory nodes further includes an address range block defining a unique address range within a unified address space; and

said address comparator is connected to said corresponding address range block and detects whether said read command includes a memory address included within said unique address range of said address range block.

15. The data processing apparatus of claim 12, further comprising:

a constant read data source connected to said read data input of said first memory node supplying predetermined constant read data.

16. The data processing apparatus of claim 12, wherein:

said command output of said last memory node is unconnected.

17. The data processing apparatus of claim 12 wherein:

said master node further capable of initializing data transfer operations by generation of a write command including an indication of one of the plurality of memory nodes, write data and a memory address;

each memory node wherein

said memory further having a data input, said memory writing data therein to addressed memory locations corresponding to an address received at said address input,

said command input further receiving write data from a prior memory node in said closed loop, said first memory node receiving said write data generated by said master node, and

said command output further supplying said received write data to a next memory node in said closed loop;

said command decoder supplying said received address to said address input of said memory and supplying said write data to a data input of said memory responsive to a received write command upon receipt of said match signal.

18. The data processing apparatus of claim 12, wherein:

each of said memory nodes further includes a data processor.

19. The data processing apparatus of claim 15, wherein:

said constant read data source supplies said predetermined constant read data consisting of all 1'"'"'s.

20. The data processing apparatus of claim 15, wherein:

said constant read data source supplies said predetermined constant read data consisting of all 0'"'"'s.

21. The data processing apparatus of claim 17, wherein:

said write data of said command output of said last memory node is unconnected.

22. A method of data transfer among a plurality of nodes comprising the steps of:

initializing transfer operations from a master node, said initializing including generating a write command including an indication of one of the plurality of nodes, write data and a memory address;

disposing the plurality of nodes in closed loop having a first node and a last node;

passing a received write command including said indication of one of the plurality of nodes, said write data and said memory address from each node to a next node in said closed loop, the first node of the plurality of nodes receiving said write command generated by the master node; and

determining at each node whether a write command received from a prior node includes an indication of one of the plurality of nodes corresponding to that node, if so writing said write data of said write command to a memory at an address corresponding to said memory address of said write command and passing said write command including said indication of one of the plurality of nodes, said write data and said memory address to said next node in said closed loop.

23. The method of claim 22, further comprising:

discarding at said last node said write command including said indication of one of said plurality of nodes, said write data and said memory address following determining at said last node whether said write command includes an indication of one of the plurality of nodes corresponding to the last node and if so writing said write data of said write command to a memory at an address corresponding to said memory address of said write command.

24. The method of claim 22, wherein:

said step of generating a write command including an indication of one of the plurality of nodes generates a node number;

said method further includes assigning a unique node number to each of said plurality of nodes; and

said step of determining whether a write command includes an indication of one of the plurality of nodes corresponding to that node includes determining if said node number of said write command corresponds to said node number assigned to that node.

25. The method of claim 22, wherein:

said step of generating a write command including an indication of one of the plurality of nodes generates a memory address within a unified address space;

said method further includes assigning a unique subset of said unified address space to each of said plurality of nodes; and

said step of determining whether a write command includes an indication of one of the plurality of nodes corresponding to that node includes determining if said memory address of said write command corresponds to said unique subset of said unified address space assigned to that node.

26. The method of claim 25, wherein:

said step of assigning a unique subset of said unified address space to each of said plurality of nodes includes assigning a unique coding of a predetermined number of most significant bits of said memory address; and

said step of determining whether a write command includes an indication of one of the plurality of nodes corresponding to that node includes determining if said predetermined number of most significant bits of said memory address of said write command corresponds to said unique coding assigned to that node.

27. The method of claim 25, wherein:

said step of assigning a unique subset of said unified address space to each of said plurality of nodes includes assigning a unique address range of said memory address; and

said step of determining whether a write command includes an indication of one of the plurality of nodes corresponding to that node includes determining if memory address of said write command is included within said unique address range assigned to that node.

28. A data processing apparatus comprising:

a plurality of memory nodes disposed in a closed loop having a first memory node and a last memory node;

a master node capable of initializing data transfer operations by generation of a read command including an indication of one of said plurality of memory nodes and a memory address;

each of said plurality of memory nodes having

an address input for receiving said memory address from a prior memory node in said closed loop, said first memory node receiving said memory address generated by said master node;

an address output for supplying said received memory address to a next memory node in said closed loop, said address output of said last memory node not connected,

a memory having an address input and a data output, said memory outputting data stored therein at addressed memory locations corresponding to an address received at said address input,

a command input for receiving a read command from a prior memory node in said closed loop, said first memory node receiving said read command generated by said master node;

a command output for supplying received read command to a next memory node in said closed loop, said command output of said last memory node not connected,

a read data input for receiving read data from a prior memory node in said closed loop,

a read data output for supplying read data to a next memory node in said closed loop, said last memory node supplying read data to said master node,

a node decoder generating a match signal upon detection that a received read command includes an indication of one of said plurality of memory modes corresponding to said memory node,

a multiplexor having a first input connected to said read data input, a second input connected to said data output of said memory and an output connected to said read data output, said multiplexor selectively connecting either said first input or said second input to said output, and

a command decoder connected to said memory, said node decoder, and said multiplexor, said command decoder supplying said received address to said address input of said memory and controlling said multiplexor to connect said second input to said output responsive to a received read command upon receipt of said match signal.

29. The data processing apparatus of claim 28, wherein:

each read command includes an indication of one of the plurality of memory nodes by a node number; and

said node decoder detects whether said node number of said received read command corresponds to a unique node number assigned to that memory node.

30. The data processing apparatus of claim 28, wherein:

each of said plurality of memory nodes store data at memory locations within a unified address space; and

said node decoder detects whether said read command includes a memory address within a unique subset of said unified address space assigned to that memory node.

31. The data processing apparatus of claim 30, wherein:

said node decoder detects whether said read command includes a memory address having a predetermined number of most significant bits corresponding to a unique coding assigned to that memory node.

32. The data processing apparatus of claim 30, wherein:

each of said plurality of memory nodes further includes an address range block defining a unique address range within said unified address space; and

said node decoder is connected to said corresponding address range block and detects whether said read command includes a memory address included within said unique address range of said address range block.

33. The data processing apparatus of claim 28, further comprising:

a constant read data source connected to said read data input of said first memory node supplying predetermined constant read data.

34. The data processing apparatus of claim 33, wherein:

said constant read data source supplies said predetermined constant read data consisting of all 1'"'"'s.

35. The data processing apparatus of claim 33, wherein:

said constant read data source supplies said predetermined constant read data consisting of all 0'"'"'s.

36. The data processing apparatus of claim 28, wherein:

said command output of said last memory node is unconnected.

37. The data processing apparatus of claim 28, wherein:

said master node further capable of initializing data transfer operations by generation of a write command including an indication of one of the plurality of memory nodes, write data and a memory address;

each memory node wherein

said memory further having a data input, said memory writing data therein to addressed memory locations corresponding to an address received at said address input,

said command input further receiving write data from a prior memory node in said closed loop, said first memory node receiving said write data generated by said master node, and

said command output further supplying said received write data to a next memory node in said closed loop;

said command decoder supplying said received address to said address input of said memory and supplying said write data to a data input of said memory responsive to a received write command upon receipt of said match signal.

38. The data processing apparatus of claim 37, wherein:

said write data of said command output of said last memory node is unconnected.

39. The data processing apparatus of claim 28, wherein:

each of said memory nodes further includes a data processor.

40. A data processing apparatus comprising:

a plurality of memory nodes disposed in a closed loop having a first memory node and a last memory node;

a master node capable of initializing data transfer operations by generation of a write command including an indication of one of said plurality of memory nodes, write data and a memory address;

each of said plurality of memory nodes having

an address input for receiving said memory address from a prior memory node in said closed loop, said first memory node receiving said memory address generated by said master node;

an address output for supplying said received memory address to a next memory node in said closed loop, said address output of said last memory node not connected,

a memory having an address input and a data input, said memory writing data therein to addressed memory locations corresponding to an address received at said address input,

a command input for receiving a write command from a prior memory node in said closed loop, said first memory node receiving said write command generated by said master node;

a command output for supplying received write command to a next memory node in said closed loop, said command output of said last memory node not connected,

a write data input for receiving write data from a prior memory node in said closed loop,

a write data output for supplying write data to a next memory node in said closed loop,

a node decoder generating a match signal upon detection that a received write command includes an indication of said memory node, and

a command decoder connected to said memory and said node decoder, said command decoder supplying said received address to said address input of said memory and supplying said write data to said data input of said memory responsive to a received write command upon receipt of said match signal.

41. The data processing apparatus of claim 40, wherein:

said write data output of said command output of said last memory node is unconnected.

42. The data processing apparatus of claim 40, wherein:

each write command includes an indication of one of the plurality of memory nodes by a node number; and

said node decoder detects whether said node number of said received write command corresponds to a unique node number assigned to that memory node.

43. The data processing apparatus of claim 40, wherein:

each of said plurality of memory nodes store data at memory locations within a unified address space; and

said node decoder detects whether said write command includes a memory address within a unique subset of said unified address space assigned to that memory node.

44. The data processing apparatus of claim 43, wherein:

said node decoder detects whether said write command includes a memory address having a predetermined number of most significant bits corresponding to a unique coding assigned to that memory node.

45. The data processing apparatus of claim 43, wherein:

each of said plurality of memory nodes further includes an address range block defining a unique address range within said unified address space; and

said node decoder is connected to said corresponding address range block and detects whether said write command includes a memory address included within said unique address range of said address range block.

46. The data processing apparatus of claim 40, wherein:

each of said memory nodes further includes a data processor.