Top/bottom symmetrical protection scheme for flash

• US 6,654,847 B1
• Filed: 06/30/2000
• Issued: 11/25/2003
• Est. Priority Date: 06/30/2000
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F., Widmer, Kevin C.
• Primary Examiner(s): Thai, Tuan V.
• Application Number:
  US09/608,256
• Time in Patent Office: 1,243 Days
• Field of Search: 711/100, 711/103, 711/154, 711/163, 365/185.04, 365/185.11
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells

Abstract

A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device can comprise an array of memory cells having N addressable sectors, and control circuitry to control erase or write operations on the array of memory cells. Protection circuitry can be coupled to the control circuitry to selectively prevent erase or write operations from being performed on both first and last sectors of the N addressable sectors. The protection circuitry can comprise a multi-bit register having a first bit corresponding to the first sector and a second bit corresponding to the last sector.

Claims

1. A synchronous memory device comprising:

an array of memory cells having N addressable sectors;

control circuitry to control erase or write operations on the array of memory cells; and

protection circuitry coupled to the control circuitry to selectively prevent erase or write operations from being performed on both first and last sectors of the N addressable sectors, the protection circuitry comprising voltage detection circuitry coupled to an external connection such that erase and write operations are disabled until a voltage above a memory device supply voltage level is detected on the external connection.

2. The synchronous memory device of claim 1 wherein the first or last sectors contain processor boot data.

3. The synchronous memory device of claim 1 wherein the protection circuitry allows either an erase or write operation to be performed on the first or last sector in response to an elevated voltage signal present on an external connection.

4. The synchronous memory device of claim 1 wherein the protection circuitry comprises a multi-bit register having a first bit corresponding to the first sector and a second bit corresponding to the last sector, and the control circuitry prevents erase or write operations to the first and last sectors when the first and second bits are programmed to a first data state.

5. The synchronous memory device of claim 4 wherein the multi-bit register is a non-volatile register.

6. The synchronous memory device of claim 4 wherein the multi-bit register is volatile register coupled to a multi-bit non-volatile register.

7. The synchronous memory device of claim 1 wherein the external connection is an address connection of the synchronous memory device.

8. The synchronous memory device of claim 1 wherein the protection circuitry allows erase or write operations to be performed on both first and last sectors of the N addressable sectors until a software command is issued by a user.

9. The synchronous memory device of claim 8 wherein the software command triggers the protection circuitry.

10. A synchronous memory device comprising:

an array of memory cells having N addressable sectors;

control circuitry to control erase or write operations on the array of memory cells; and

protection circuitry coupled to the control circuitry to selectively prevent erase or write operations from being performed on a least significant sector and a most significant sector of the N addressable sectors, the protection circuitry comprises a signal monitoring circuit to determine if an electronic key is provided to the synchronous memory device on an external connection.

11. The synchronous memory device of claim 10 wherein the protection circuitry comprises an N-bit register wherein each one of the N-bits corresponds to one of the N sectors and can be programmed to either a first or second data state.

12. The synchronous memory device of claim 11 wherein the control circuitry allows erase or write operations to a sector if the corresponding register bit is in the first state, and the control circuitry prohibits erase or write operations to the sector if the corresponding register bit is in the second state.

13. The synchronous memory device of claim 10 wherein the electronic key is an elevated voltage, greater than a device supply voltage, provided on an external connection.

14. A method of protecting memory locations in a synchronous flash memory device, the method comprising:

programming a data register having data bits corresponding to the memory locations to either a first or second data state;

preventing erase or write operations to a first memory location if a corresponding data bit is in the first state; and

allowing the erase or write operations to the first memory location if the corresponding data bit is in the second state and a voltage level on a device input connection is greater than a device supply voltage level.

15. The method of claim 14 wherein the synchronous flash memory device comprises a memory array having a plurality of addressable sectors that define the memory locations.

16. The method of claim 14 wherein the data register is a volatile register and programming the data register comprises transferring data from a non-volatile register.

17. A method of preventing accidental loss of data in a memory device, the method comprising;

programming a register circuit to a first data state;

authorizing write and erase operations on the memory device while the register circuit is programmed to the first data state;

programming the register circuit to a second data state;

activating a protection circuit in response to programming the register circuit to the second data state; and

prohibiting write and erase operations on the memory device while the register circuit is programmed to the second data state unless an electronic key is provided to the protection circuit from a device external connection.

18. The method of claim 17 wherein the electronic key is a voltage signal on a preselected external connection that has a voltage level above a predetermined threshold.

19. The method of claim 17 wherein the register is a non-volatile register.

20. The method of claim 17 wherein the register is a volatile register and programming the register circuit comprises transferring data from a non-volatile register to the volatile register circuit.

21. A memory system comprising:

a memory controller; and

a synchronous flash memory device coupled to the memory controller, the synchronous memory device comprises,

an array of memory cells having N addressable sectors,

control circuitry to control erase or write operations on the array of memory cells, and

protection circuitry coupled to the control circuitry to selectively prevent erase or write operations from being performed on both first and last sectors of the N addressable sectors, wherein the protection circuitry allows either the erase or the write operation to be performed by the memory controller on the first or last sector in response to an elevated voltage signal provided by the memory controller on an external connection of the synchronous flash memory device.

22. The memory system of claim 21 wherein the first or last sectors contain system boot data.

23. The memory system of claim 21 wherein the protection circuitry comprises a multi-bit register having a first bit corresponding to the first sector and a second bit corresponding to the last sector, and the control circuitry prevents erase or write operations to the first and last sectors when the first and second bits are programmed to a first data state.

24. A synchronous memory device comprising:

an array of memory cells having N addressable sectors;

control circuitry to control erase or write operations on the array of memory cells; and

protection circuitry coupled to the control circuitry to selectively prevent erase or write operations from being performed on both first and last sectors of the N addressable sectors, the protection circuitry comprising;

voltage detection circuitry coupled to an external connection to detect a voltage presented on the external connection that is above a threshold voltage level; and

a multi-bit register having a first bit corresponding to the first sector and a second bit corresponding to the last sector, wherein erase and write operations can be performed by the control circuitry when the first and last bits are in a first data state and erase and write operations are prevented from being performed by the control circuitry when the first and last bits are in a second data state unless a voltage provided on the external connection is above the threshold voltage level.

25. A synchronous memory device comprising:

an array of memory cells having N addressable sectors;

control circuitry to control erase or write operations on the array of memory cells; and

protection circuitry coupled to the control circuitry to selectively prevent erase or write operations from being performed on both first and last sectors of the N addressable sectors, the protection circuitry comprising;

voltage detection circuitry coupled to an external connection to detect a voltage presented on the external connection that is above a threshold voltage level and provide an output signal; and

a multi-bit register having a first bit corresponding to the first sector and a second bit corresponding to the last sector, wherein the first and second bits can be programmed to either a first or second data state, the control circuitry allows erase and write operations to the first and last sectors when the first and second bits are programmed to the first data state, the control circuitry prevents erase and write operations in response to the output signal from the voltage detection circuit when the first and second bits are in the second data state.