Top/bottom symmetrical protection scheme for flash
DCFirst Claim
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1. A synchronous memory device comprising:
- an array of memory cells having N addressable sectors;
control circuitry to control erase or write operations on the array of memory cells; and
protection circuitry coupled to the control circuitry to selectively prevent erase or write operations from being performed on both first and last sectors of the N addressable sectors, the protection circuitry comprising voltage detection circuitry coupled to an external connection such that erase and write operations are disabled until a voltage above a memory device supply voltage level is detected on the external connection.
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Abstract
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device can comprise an array of memory cells having N addressable sectors, and control circuitry to control erase or write operations on the array of memory cells. Protection circuitry can be coupled to the control circuitry to selectively prevent erase or write operations from being performed on both first and last sectors of the N addressable sectors. The protection circuitry can comprise a multi-bit register having a first bit corresponding to the first sector and a second bit corresponding to the last sector.
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Citations
25 Claims
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1. A synchronous memory device comprising:
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an array of memory cells having N addressable sectors;
control circuitry to control erase or write operations on the array of memory cells; and
protection circuitry coupled to the control circuitry to selectively prevent erase or write operations from being performed on both first and last sectors of the N addressable sectors, the protection circuitry comprising voltage detection circuitry coupled to an external connection such that erase and write operations are disabled until a voltage above a memory device supply voltage level is detected on the external connection. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A synchronous memory device comprising:
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an array of memory cells having N addressable sectors;
control circuitry to control erase or write operations on the array of memory cells; and
protection circuitry coupled to the control circuitry to selectively prevent erase or write operations from being performed on a least significant sector and a most significant sector of the N addressable sectors, the protection circuitry comprises a signal monitoring circuit to determine if an electronic key is provided to the synchronous memory device on an external connection. - View Dependent Claims (11, 12, 13)
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14. A method of protecting memory locations in a synchronous flash memory device, the method comprising:
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programming a data register having data bits corresponding to the memory locations to either a first or second data state;
preventing erase or write operations to a first memory location if a corresponding data bit is in the first state; and
allowing the erase or write operations to the first memory location if the corresponding data bit is in the second state and a voltage level on a device input connection is greater than a device supply voltage level. - View Dependent Claims (15, 16)
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17. A method of preventing accidental loss of data in a memory device, the method comprising;
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programming a register circuit to a first data state;
authorizing write and erase operations on the memory device while the register circuit is programmed to the first data state;
programming the register circuit to a second data state;
activating a protection circuit in response to programming the register circuit to the second data state; and
prohibiting write and erase operations on the memory device while the register circuit is programmed to the second data state unless an electronic key is provided to the protection circuit from a device external connection. - View Dependent Claims (18, 19, 20)
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21. A memory system comprising:
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a memory controller; and
a synchronous flash memory device coupled to the memory controller, the synchronous memory device comprises, an array of memory cells having N addressable sectors, control circuitry to control erase or write operations on the array of memory cells, and protection circuitry coupled to the control circuitry to selectively prevent erase or write operations from being performed on both first and last sectors of the N addressable sectors, wherein the protection circuitry allows either the erase or the write operation to be performed by the memory controller on the first or last sector in response to an elevated voltage signal provided by the memory controller on an external connection of the synchronous flash memory device. - View Dependent Claims (22, 23)
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24. A synchronous memory device comprising:
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an array of memory cells having N addressable sectors;
control circuitry to control erase or write operations on the array of memory cells; and
protection circuitry coupled to the control circuitry to selectively prevent erase or write operations from being performed on both first and last sectors of the N addressable sectors, the protection circuitry comprising;
voltage detection circuitry coupled to an external connection to detect a voltage presented on the external connection that is above a threshold voltage level; and
a multi-bit register having a first bit corresponding to the first sector and a second bit corresponding to the last sector, wherein erase and write operations can be performed by the control circuitry when the first and last bits are in a first data state and erase and write operations are prevented from being performed by the control circuitry when the first and last bits are in a second data state unless a voltage provided on the external connection is above the threshold voltage level.
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25. A synchronous memory device comprising:
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an array of memory cells having N addressable sectors;
control circuitry to control erase or write operations on the array of memory cells; and
protection circuitry coupled to the control circuitry to selectively prevent erase or write operations from being performed on both first and last sectors of the N addressable sectors, the protection circuitry comprising;
voltage detection circuitry coupled to an external connection to detect a voltage presented on the external connection that is above a threshold voltage level and provide an output signal; and
a multi-bit register having a first bit corresponding to the first sector and a second bit corresponding to the last sector, wherein the first and second bits can be programmed to either a first or second data state, the control circuitry allows erase and write operations to the first and last sectors when the first and second bits are programmed to the first data state, the control circuitry prevents erase and write operations in response to the output signal from the voltage detection circuit when the first and second bits are in the second data state.
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Specification