Automated system for inserting and reading of probe points in silicon embedded testbenches

• US 6,654,919 B1
• Filed: 04/17/2000
• Issued: 11/25/2003
• Est. Priority Date: 04/17/2000
• Status: Expired due to Fees

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Watkins, Daniel
• Primary Examiner(s): Moise, Emmanuel L.
• Assistant Examiner(s): LAMARRE, GUY J
• Application Number:
  US09/550,764
• Time in Patent Office: 1,317 Days
• Field of Search: 714/724, 714/733, 714/32-33, 714/38, 714/725, 714/734, 714/741, 713/100, 703/26, 703/28, 703/23, 716/1, 716/3, 716/4, 716/5, 716/13-18, 717/174-178, 348/180, 345/723, 324/537, 324/758, 374/1, 374/130, 250/306, 250/307, 250/309, 257/48, 257/690
• US Class Current: 714/733
• CPC Class Codes: G01R 31/318314 Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages simulation software G01R31/318357; emulators G06F11/261
• CPC Class Codes: G01R 31/318378 of patterns for devices arranged in a network
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56004 Pattern generation

Abstract

A method for inserting and reading probe points in a silicon embedded testbench comprising the steps of (a) reading a simulation list of probe points, (b) enabling access to the list of probe points, (c) generating a core, and (d) displaying or comparing the probe points.

Claims

1. A method for inserting and reading one or more probe points in a silicon embedded testbench comprising the steps of:

(a) inserting and reading a simulation list of probe points;

(b) enabling access to the list of probe points;

(c) generating a core;

(d) displaying or comparing the probe points;

(e) embedding probe point capability from simulation probe point information; and

(f) systematically programming embedded probe type real time and stored state information into the silicon with said testbench.

2. The method according to claim 1, further comprising the step of:

prior to step (c), filtering said list.

3. The method according to claim 1, wherein said core is built in silicon.

4. The method according to claim 3, wherein a sub-core may be part of an on-chip bus that may present information off chip.

5. The method according to claim 1, wherein the probe points are written to and read from prior to or during a silicon functional operation.

6. The method according to claim 1, further comprising:

uploading probe point results in a simulation testbench or analysis tool; and

optionally loading the simulation testbench or analysis tool with one or more initial statement information parameters received from the simulations.

7. The method according to claim 1, further comprising:

generating an extensive set of probe core generator parameters, reflecting common simulator capabilities including capture changes only or capture starting at a specific time point.

8. The method according to claim 1, wherein step (e) comprises:

embedding probe point capability, directly or indirectly, from said simulation probe point information.

9. The method according to claim 1, further comprising the step of:

implementing an extensive list of probe core generator parameters allowing optimum access to probe points in silicon with minimal impact on design.

10. The method according to claim 9, further comprising the step of:

automatically and incrementally building to add or subtract probe points.

11. The method according to claim 10, wherein said probe points provide operation information useful to a system on a chip verification.

12. The method according to claim 10, wherein:

(a) said testbench represents models that are for verification, performance or analysis; and

(b) said testbench is not intended as part of a final product operation.

13. The method according to claim 12, wherein one or more reusable testbench components can be shared by one or more second testbenches.

14. The method according to claim 13, wherein said second testbenches are embedded with said probe points that are common and specific.

15. The method according to claim 14, further comprising the step of:

implementing an evaluation system to leverage embedded testbench probes.

16. The method according to claim 15, further comprising the step of:

implementing menu programming for extracting probe information available from silicon.

17. The method according to claim 16, wherein a test suite can be re-launched on a mis-compare with relevant probe point information capture enabled.

18. The method according to claim 16, wherein a performance probe analysis can be launched for:

(a) running specific testbench sequences to assess performance;

(b) performing a self-test; and

(c) gathering statistics on performance.

19. The method according to claim 18, further comprising the step of:

loading program memory of a module or a chip set.

20. The method according to claim 19, further comprising the steps of:

extracting probe information; and

loading simulation information.

21. The method according to claim 20, further comprising the step of:

conducting field diagnosis with said embedded testbenches comprising said probe points accessible to the system.

22. An apparatus comprising:

means for reading a simulation list of probe points;

means for enabling access to the list of probe points;

means for generating a core;

means for displaying or comparing the probe points;

means for embedding probe point capability from simulation probe point information; and

means for systematically programming embedded probe type real time and stored state information into the silicon with said testbench.

23. An apparatus comprising:

a first module configured to read a simulation list of probe points and enable access to said list of probe points;

a second module configured to generate a core;

a third module configured to display or compare probe points;

a fourth module configured to embed probe point capability from simulation probe point information; and

a fifth module configured to systematically program embedded probe type real time and stored state information into the silicon with said testbench.