FeRAM capacitor post stack etch clean/repair

• US 6,656,748 B2
• Filed: 04/18/2002
• Issued: 12/02/2003
• Est. Priority Date: 01/31/2002
• Status: Expired due to Term

• Current Assignee: Broadcom International Pte Ltd. (Broadcom, Inc.)
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hall, Lindsey H., Summerfelt, Scott R.
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US10/125,662
• Publication Number:
  US 20030143800A1
• Time in Patent Office: 593 Days
• Field of Search: 438/3, 438/4, 438/240, 438/250, 438/253, 438/254, 438/255, 438/393, 438/396, 438/397, 438/398, 438/689, 438/785, 438/795, 257/303, 257/310
• US Class Current: 438/3
• CPC Class Codes: H01L 21/02197 the material having a perovskite structure, e.g. BaTiO3
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/31691 with perovskite structure
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region
• CPC Class Codes: H10B 53/40 characterised by the peripheral circuit region

Abstract

The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl₃ etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF₃ to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.

Claims

1. A method of performing a post capacitor stack etch clean for a ferroelectric memory cell, comprising:

forming a bottom electrode layer, a PZT ferroelectric layer, and a top electrode layer over a substrate;

etching the top electrode layer, the PZT ferroelectric layer, and the bottom electrode layer to form a capacitor stack, wherein the PZT ferroelectric layer has damage associated therewith due to the etching of the PZT ferroelectric layer;

annealing the etched capacitor stack in a chamber having a lead source and oxygen, wherein a vapor pressure of the lead source is greater than a vapor pressure of the etched PZT ferroelectric layer, thereby facilitating a vapor transport of lead from the lead source to the etched PZT ferroelectric layer for repair thereof.

2. The method of claim 1, wherein annealing the etched capacitor stack comprises maintaining a temperature in the chamber in a range of about 450°

C. or more and about 650°

C. or less.

3. The method of claim 2, wherein the temperature in the chamber comprises 600°

C.

4. The method of claim 1, wherein the lead source and oxygen comprise a PbO, PbTiO₃ or PZT source material.

5. The method of claim 1, wherein the chamber is a chemical vapor deposition chamber or a furnace chamber, and wherein the source material comprises a Pb metalorganic precursor, and wherein the Pb metalorganic precursor reacts with the oxygen to form PbO having a deposition rate which is less than its evaporation rate, thereby ensuring vapor transport and not deposition.

6. A method of performing a post capacitor stack etch treatment for a ferroelectric memory device, comprising:

forming a bottom electrode diffusion barrier layer over a substrate;

forming a bottom electrode layer, a PZT ferroelectric layer, and a top electrode layer in succession over the bottom electrode diffusion barrier layer;

patterning a portion of the top electrode layer, the PZT ferroelectric layer and the bottom electrode layer in succession to form a capacitor stack overlying the bottom electrode diffusion barrier layer;

repairing damage to the PZT ferroelectric layer due to the patterning of the capacitor stack, wherein the repairing comprises introducing lead into the PZT ferroelectric layer after the patterning thereof; and

patterning a portion of the bottom electrode diffusion barrier layer which does not underlie the capacitor stack.

7. The method of claim 6, wherein repairing the damage to the PZT ferroelectric layer comprises annealing the capacitor stack in a chamber having a lead source and oxygen.

8. The method of claim 7, wherein repairing the damage to the PZT ferroelectric layer further comprises maintaining a vapor pressure of the lead source is greater than a vapor pressure of the patterned PZT ferroelectric layer.

9. The method of claim 7, wherein the lead source and oxygen comprise a PbO, PbTiO₃ or PZT source material.

10. The method of claim 7, wherein annealing the etched capacitor stack comprises maintaining a temperature in the chamber in a range of about 450°

C. or more and about 650°

C. or less.

11. The method of claim 10, wherein the temperature in the chamber comprises 600°

C.

12. The method of claim 6, wherein repairing the PZT ferroelectric layer comprises:

placing the substrate in a chemical vapor deposition chamber or a furnace chamber; and

subjecting the substrate to a source material which comprises a Pb metalorganic precursor, wherein the Pb metalorganic precursor reacts with the oxygen to form PbO having a deposition rate which is less than its evaporation rate, thereby ensuring vapor transport and not deposition.

13. The method of claim 6, wherein the patterning of the bottom electrode diffusion barrier layer occurs after repairing the damage to the PZT ferroelectric layer.

14. A method of performing a post capacitor stack etch treatment for a ferroelectric memory device, comprising:

forming a bottom electrode diffusion barrier layer over a substrate;

forming a bottom electrode layer, a PZT ferroelectric layer, and a top electrode layer in succession over the bottom electrode diffusion barrier layer;

patterning a portion of the top electrode layer, the PZT ferroelectric layer and the bottom electrode layer in succession to form a capacitor stack overlying the bottom electrode diffusion barrier layer;

introducing lead into the patterned PZT ferroelectric layer; and

patterning a portion of the bottom electrode diffusion barrier layer which does not underlie the capacitor stack after formation of the capacitor stack.