Passivation structure for flash memory and method for fabricating same

• US 6,656,778 B1
• Filed: 04/26/2002
• Issued: 12/02/2003
• Est. Priority Date: 04/26/2002
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lu, Chen-Chien, Lee, Tung-Ta, Chen, I-Yueh, Chen, Jung-Chieh
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Schillinger, Laura M
• Application Number:
  US10/133,142
• Time in Patent Office: 585 Days
• Field of Search: 257/314, 257/315, 257/316, 257/321, 257/640, 257/72, 438/257, 438/595, 438/258, 438/972, 438/159, 438/165, 438/278, 438/637, 438/185, 438/201, 438/210, 438/211
• US Class Current: 438/159
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02203 the layer being porous
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/3144 on silicon

Abstract

A passivation structure for a semiconductor device includes a high ultraviolet transmittance silicon nitride (UV-SiN) layer. This UV-SiN layer substantially conformally overlies a plurality of top metal lines, which are formed over a semiconductor substrate, such that topographical hollows are defined between adjacent top metal lines. A spin-on glass (SOG) material fills in the topographical hollows. A silicon oxynitride (SiON) layer having a thickness in a range from about 8,000 angstroms to about 10,000 angstroms overlies the UV-SiN layer and the SOG material. A method for forming the passivation structure also is described.

Claims

1. A passivation structure for a semiconductor device, comprising:

a plurality of top metal lines overlying a substrate;

a high ultraviolet transmittance silicon nitride layer substantially conformally overlying the plurality of top metal lines such that portions of a top surface of the high ultraviolet transmittance silicon nitride layer define a plurality of topographical hollows between adjacent top metal lines;

a spin-on glass material overlying the portions of the high ultraviolet transmittance silicon nitride layer that define the plurality of topographical hollows; and

a silicon oxynitride layer overlying the high ultraviolet transmittance silicon nitride layer and the spin-on glass material.

2. The passivation structure of claim 1, wherein the high ultraviolet transmittance silicon nitride layer has a thickness of about 4,000 angstroms.

3. The passivation structure of claim 1, wherein the spin-on glass material has a thickness of about 3,400 angstroms.

4. The passivation structure of claim 1, wherein the silicon oxynitride layer has a thickness in a range from about 8,000 angstroms to about 10,000 angstroms.

5. The passivation structure of claim 1, wherein the spin-on glass material is a material selected from the group consisting of silicate-based materials and siloxane-based materials.

6. The passivation structure of claim 1, wherein the semiconductor device is a flash memory.