Transistor having variable width gate electrode and method of manufacturing the same

• US 6,656,808 B2
• Filed: 09/05/2001
• Issued: 12/02/2003
• Est. Priority Date: 09/05/2000
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwean, Sung-Un
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): GARCIA, JOANNIE A
• Application Number:
  US09/945,723
• Publication Number:
  US 20020027254A1
• Time in Patent Office: 818 Days
• Field of Search: 438/305, 438/585, 438/978, 438/FOR.188, 438/FOR.458, 438/FOR.492, 257/408, 257/29.135
• US Class Current: 438/305
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: Y10S 438/978 forming tapered edges on substrate or adjacent layers

Abstract

A transistor includes a substrate and a gate electrode formed on the substrate and having a wider upper portion than lower portion. A spacer is formed on the side wall of the gate electrode from the upper portion to the lower portion of the gate electrode. A first impurity doped region is formed at an upper portion of the substrate and a second impurity doped region having a higher concentration is formed at a narrower and deeper region than the first impurity doped region.

Claims

1. A transistor comprising:

a substrate;

a gate electrode formed on a horizontal surface of said substrate, said gate electrode having an upper portion and a lower portion, wherein a vertical side-wall of said lower portion is concave, and wherein a horizontal width of said upper portion is greater than a horizontal width of said lower portion;

a spacer formed on a side wall of said gate electrode from said upper portion to said lower portion thereof;

a first impurity doped region formed at an upper portion of said substrate; and

a second impurity doped region underlying said first impurity doped region,

wherein said second impurity doped region has an impurity concentration higher than said first impurity doped region, and

wherein said second impurity doped region is narrower than said first impurity doped region.

2. A transistor as claimed in claim 1, wherein the ratio of the horizontal width of said upper portion to the horizontal width of said lower portion of said gate electrode is in a range of about 1.3-2.5:

1.

3. A transistor as claimed in claim 1, wherein the horizontal width of said lower portion of said gate electrode is no greater than about 0.13 μ

m.

4. A transistor as claimed in claim 1, wherein a height of said gate electrode is in a range of about 1500-2500 Å

.

5. A transistor as claimed in claim 1, further comprising a metal silicide compound formed on said gate electrode and said substrate.

6. A transistor as claimed in claim 1, wherein said spacer includes a bottom surface facing said horizontal surface of said substrate, and said transistor further comprising a nitride layer interposed between said bottom surface of said spacer and said horizontal surface of said substrate.

7. A method of manufacturing a transistor comprising:

providing a substrate;

forming a gate electrode on a horizontal surface of said substrate, said gate electrode having an upper portion and a lower portion, wherein a vertical side-wall of said lower portion is concave, and wherein a horizontal width of said upper portion is greater than a horizontal width of said lower portion;

forming a first impurity doped region in said substrate by doping a first impurity having a low concentration and using said gate electrode as a mask;

forming a spacer composed of a nitride compound on a side wall of said gate electrode from said upper portion to said lower portion; and

forming a second impurity doped region in said substrate by doping a second impurity having a higher concentration than that of said first impurity, and using said spacer as a mask.

15. A method as claimed in claim 7, wherein after forming a second impurity doped region, further comprising:

depositing at least one metal selected from the group consisting of Co, Ti and Ni on said substrate and said gate electrode to form a metal layer; and

implementing a heat treating process on said metal layer to form a metal silicide region on said gate electrode and said substrate.

16. A method as claimed in claim 7, wherein during said forming of said gate electrode, the horizontal width of said lower portion of said gate electrode is no greater than about 0.13 μ

m.

17. A method as claimed in claim 16, wherein during said forming of said gate electrode, a ratio between the horizontal width of said upper portion to the horizontal width of said lower portion of said gate electrode is in a range of about 1.3-2.5:

1.

8. A method of manufacturing a transistor comprising:

providing a substrate;

forming a gate electrode on said substrate, said gate electrode having an upper portion and a lower portion, and wherein a horizontal width of said upper portion is greater than a horizontal width of said lower portion;

forming a first impurity doped region in said substrate by doping a first impurity having a low concentration and using said gate electrode as a mask;

forming a spacer composed of a nitride compound on a side wall of said gate electrode from said upper portion to said lower portion; and

forming a second impurity doped region in said substrate by doping a second impurity having a higher concentration than that of said first impurity, and using said spacer as a mask;

wherein said forming the gate electrode comprises;

forming, sequentially, a nitride layer, an oxide layer and a photoresist pattern on a substrate;

forming an oxide pattern by etching said oxide layer using said photoresist pattern as a mask, wherein said etching exposes the nitride layer;

forming a sacrificial spacer on a side wall of said oxide pattern;

removing the exposed portion of the nitride layer between the sacrificial spacer to expose said substrate;

forming a thermal oxide layer on the exposed portion of said substrate between the sacrificial spacer;

depositing a polysilicon layer on the whole surface of said substrate and said oxide layer;

planarizing said polysilicon layer; and

removing said sacrificial spacer and said oxide layer.

9. A method as claimed in claim 8, wherein said sacrificial spacer is formed by depositing a same material as the oxide layer and implementing an etch back process until said nitride layer is exposed.

10. A method as claimed in claim 8, further comprising

forming a nitride pattern after forming said oxide layer and before forming said photoresist pattern, wherein said nitride pattern is formed by depositing another nitride layer on said oxide layer, and after forming said photoresist pattern, then etching said another nitride layer using said photoresist pattern as a mask, and

wherein said planarizing process is carried out by a CMP (chemical mechanical polishing) method using said nitride pattern as an etch stopping layer.

11. A method as claimed in claim 10, wherein during said forming said another nitride layer, further comprising selecting one of SiN and SiON for a material for said another nitride layer.

12. A method as claimed in claim 10, wherein an etching selectivity of said another nitride layer with respect to said oxide layer during the forming of said nitride pattern and oxide pattern is in a range of about 30:

1-5;

1.

13. A method as claimed in claim 8, wherein said planarizing process is carried out by an etch back method until said polysilicon reaches a predetermined thickness.

14. A method as claimed in claim 8, wherein during said forming of said oxide layer, further comprising selecting a material for said oxide layer from a group consisting of SiO₂, HTO and Al₂O₃.

18. A method of manufacturing a transistor comprising:

forming, sequentially, a nitride layer, an oxide layer and a photoresist pattern on a substrate;

forming an oxide pattern by etching said oxide layer using said photoresist pattern as a mask, wherein said etching exposes the nitride layer;

forming a sacrificial spacer on a side wall of said oxide pattern;

removing the exposed portion of the nitride layer between the sacrificial spacer to expose said substrate;

forming a thermal oxide layer on the exposed portion of said substrate between the sacrificial spacer;

forming a polysilicon layer by depositing polysilicon on a whole surface of said substrate;

planarizing said polysilicon layer;

forming a gate electrode having an upper portion and a lower portion, by removing said sacrificial spacer and said oxide layer, wherein a horizontal width of the upper portion is greater than a horizontal width of a lower portion;

doping a first impurity in said substrate at an angle which is offset from a direction perpendicular to a surface of the substrate, using said gate electrode as a mask; and

doping a second impurity in said substrate having a higher concentration than that of the first impurity, at an angle which is coincident with the direction perpendicular to the surface of the substrate, using said gate electrode as a mask.

19. A method as claimed in claim 18, wherein during said doping of the first impurity, said predetermined angle is ±

7°

.

20. A method as claimed in claim 18, further comprising:

forming a spacer on a side wall of said gate electrode from the upper portion to the lower portion thereof, after said doping said first impurity and before said doping said second impurity;

depositing at least one metal selected from the group consisting of Co, Ti and Ni on said substrate and said gate electrode to form a metal layer; and

implementing a heat treating process on said metal layer to form a metal silicide region on said gate electrode and said substrate.