Transistor having variable width gate electrode and method of manufacturing the same
First Claim
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1. A transistor comprising:
- a substrate;
a gate electrode formed on a horizontal surface of said substrate, said gate electrode having an upper portion and a lower portion, wherein a vertical side-wall of said lower portion is concave, and wherein a horizontal width of said upper portion is greater than a horizontal width of said lower portion;
a spacer formed on a side wall of said gate electrode from said upper portion to said lower portion thereof;
a first impurity doped region formed at an upper portion of said substrate; and
a second impurity doped region underlying said first impurity doped region, wherein said second impurity doped region has an impurity concentration higher than said first impurity doped region, and wherein said second impurity doped region is narrower than said first impurity doped region.
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Abstract
A transistor includes a substrate and a gate electrode formed on the substrate and having a wider upper portion than lower portion. A spacer is formed on the side wall of the gate electrode from the upper portion to the lower portion of the gate electrode. A first impurity doped region is formed at an upper portion of the substrate and a second impurity doped region having a higher concentration is formed at a narrower and deeper region than the first impurity doped region.
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Citations
20 Claims
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1. A transistor comprising:
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a substrate;
a gate electrode formed on a horizontal surface of said substrate, said gate electrode having an upper portion and a lower portion, wherein a vertical side-wall of said lower portion is concave, and wherein a horizontal width of said upper portion is greater than a horizontal width of said lower portion;
a spacer formed on a side wall of said gate electrode from said upper portion to said lower portion thereof;
a first impurity doped region formed at an upper portion of said substrate; and
a second impurity doped region underlying said first impurity doped region, wherein said second impurity doped region has an impurity concentration higher than said first impurity doped region, and wherein said second impurity doped region is narrower than said first impurity doped region. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of manufacturing a transistor comprising:
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providing a substrate;
forming a gate electrode on a horizontal surface of said substrate, said gate electrode having an upper portion and a lower portion, wherein a vertical side-wall of said lower portion is concave, and wherein a horizontal width of said upper portion is greater than a horizontal width of said lower portion;
forming a first impurity doped region in said substrate by doping a first impurity having a low concentration and using said gate electrode as a mask;
forming a spacer composed of a nitride compound on a side wall of said gate electrode from said upper portion to said lower portion; and
forming a second impurity doped region in said substrate by doping a second impurity having a higher concentration than that of said first impurity, and using said spacer as a mask. - View Dependent Claims (15, 16, 17)
depositing at least one metal selected from the group consisting of Co, Ti and Ni on said substrate and said gate electrode to form a metal layer; and
implementing a heat treating process on said metal layer to form a metal silicide region on said gate electrode and said substrate.
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16. A method as claimed in claim 7, wherein during said forming of said gate electrode, the horizontal width of said lower portion of said gate electrode is no greater than about 0.13 μ
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17. A method as claimed in claim 16, wherein during said forming of said gate electrode, a ratio between the horizontal width of said upper portion to the horizontal width of said lower portion of said gate electrode is in a range of about 1.3-2.5:
- 1.
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8. A method of manufacturing a transistor comprising:
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providing a substrate;
forming a gate electrode on said substrate, said gate electrode having an upper portion and a lower portion, and wherein a horizontal width of said upper portion is greater than a horizontal width of said lower portion;
forming a first impurity doped region in said substrate by doping a first impurity having a low concentration and using said gate electrode as a mask;
forming a spacer composed of a nitride compound on a side wall of said gate electrode from said upper portion to said lower portion; and
forming a second impurity doped region in said substrate by doping a second impurity having a higher concentration than that of said first impurity, and using said spacer as a mask;
wherein said forming the gate electrode comprises;
forming, sequentially, a nitride layer, an oxide layer and a photoresist pattern on a substrate;
forming an oxide pattern by etching said oxide layer using said photoresist pattern as a mask, wherein said etching exposes the nitride layer;
forming a sacrificial spacer on a side wall of said oxide pattern;
removing the exposed portion of the nitride layer between the sacrificial spacer to expose said substrate;
forming a thermal oxide layer on the exposed portion of said substrate between the sacrificial spacer;
depositing a polysilicon layer on the whole surface of said substrate and said oxide layer;
planarizing said polysilicon layer; and
removing said sacrificial spacer and said oxide layer. - View Dependent Claims (9, 10, 11, 12, 13, 14)
forming a nitride pattern after forming said oxide layer and before forming said photoresist pattern, wherein said nitride pattern is formed by depositing another nitride layer on said oxide layer, and after forming said photoresist pattern, then etching said another nitride layer using said photoresist pattern as a mask, and wherein said planarizing process is carried out by a CMP (chemical mechanical polishing) method using said nitride pattern as an etch stopping layer. -
11. A method as claimed in claim 10, wherein during said forming said another nitride layer, further comprising selecting one of SiN and SiON for a material for said another nitride layer.
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12. A method as claimed in claim 10, wherein an etching selectivity of said another nitride layer with respect to said oxide layer during the forming of said nitride pattern and oxide pattern is in a range of about 30:
- 1-5;
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- 1-5;
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13. A method as claimed in claim 8, wherein said planarizing process is carried out by an etch back method until said polysilicon reaches a predetermined thickness.
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14. A method as claimed in claim 8, wherein during said forming of said oxide layer, further comprising selecting a material for said oxide layer from a group consisting of SiO2, HTO and Al2O3.
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18. A method of manufacturing a transistor comprising:
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forming, sequentially, a nitride layer, an oxide layer and a photoresist pattern on a substrate;
forming an oxide pattern by etching said oxide layer using said photoresist pattern as a mask, wherein said etching exposes the nitride layer;
forming a sacrificial spacer on a side wall of said oxide pattern;
removing the exposed portion of the nitride layer between the sacrificial spacer to expose said substrate;
forming a thermal oxide layer on the exposed portion of said substrate between the sacrificial spacer;
forming a polysilicon layer by depositing polysilicon on a whole surface of said substrate;
planarizing said polysilicon layer;
forming a gate electrode having an upper portion and a lower portion, by removing said sacrificial spacer and said oxide layer, wherein a horizontal width of the upper portion is greater than a horizontal width of a lower portion;
doping a first impurity in said substrate at an angle which is offset from a direction perpendicular to a surface of the substrate, using said gate electrode as a mask; and
doping a second impurity in said substrate having a higher concentration than that of the first impurity, at an angle which is coincident with the direction perpendicular to the surface of the substrate, using said gate electrode as a mask. - View Dependent Claims (19, 20)
forming a spacer on a side wall of said gate electrode from the upper portion to the lower portion thereof, after said doping said first impurity and before said doping said second impurity;
depositing at least one metal selected from the group consisting of Co, Ti and Ni on said substrate and said gate electrode to form a metal layer; and
implementing a heat treating process on said metal layer to form a metal silicide region on said gate electrode and said substrate.
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Specification