Top layers of metal for high performance IC's

• US 6,657,310 B2
• Filed: 10/09/2001
• Issued: 12/02/2003
• Est. Priority Date: 12/21/1998
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): Pham, Long
• Application Number:
  US09/972,639
• Publication Number:
  US 20020048930A1
• Time in Patent Office: 784 Days
• Field of Search: 438/637, 438/638, 438/618, 438/622, 438/623, 438/624, 438/625, 257/778, 257/691, 257/692, 257/758, 257/759, 257/760
• US Class Current: 257/778
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/0676 comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Claims

1. A semiconductor device structure comprising:

a semiconductor substrate having semiconductor devices formed thereon;

an interconnecting metallization structure comprising lower metal lines, formed over and connected to said devices;

electrical contact points on an upper surface of said interconnecting metallization structure and connected to said interconnecting metallization structure;

a passivation layer deposited over said interconnecting metallization structure and over said electrical contact points;

openings through said passivation layer, exposing said electrical contact points; and

an upper metallization structure within said openings and over said passivation layer, comprising upper metal lines, connected to said interconnecting metallization structure, wherein said upper metal lines are substantially thicker than said lower metal lines.

2. The structure of claim 1 wherein the upper metallization structure connects portions of said interconnecting metallization structure to other portions of said interconnecting metallization structure.

3. The structure of claim 1 wherein said upper metallization structure comprises:

a plurality of insulating layers;

one or more of said upper metal lines formed between said insulating layers; and

a plurality of contact pads in an upper layer of said metallization structure, connected to one or more of said upper metal lines.

4. The structure of claim 3 wherein said upper metal lines comprise lines that are selected from the group consisting of signal lines, power buses and ground buses, or a combination thereof, and wherein said upper metal lines are substantially wider than said lower metal lines in said interconnecting metallization structure.

5. The structure of claim 1 wherein the size of said contact points is within the range of approximately 0.3 um. to 5.0 um, wherein said contact points comprise tungsten, copper (electroplated or electroless), aluminum, or polysilicon,.

6. The structure of claim 1 wherein said passivation layer comprises a layer within the range of approximately 0.15 to 2.0 um Plasma Enhanced CVD (PECVD) oxide over which a layer within the range of approximately 0.5 to 2.0 um PECVD nitride is deposited.

7. The structure of claim 1 further comprising an insulating, separating layer formed over said passivation layer, wherein said insulating, separating layer is a polymer.

8. The structure of claim 7 wherein said insulating, separating layer comprises polyimide.

9. The structure of claim 7 wherein said insulating, separating layer comprises the polymer benzocyclobutene (BCB).

10. The structure of claim 7 wherein said insulating layer is of a thickness after curing within the range of approximately 1.0 to 30 um.

11. The structure of claim 1 wherein said openings have an aspect ratio within the range of approximately 1 to 10.

12. The structure of claim 1 wherein said upper metallization system is formed to provide fan-out capability, wherein a distance separating contact points in a top layer of said upper metallization structure is greater than a distance separating electrical contact points in said interconnecting metallization structure.

13. The structure of claim 1 wherein said the number of said electrical contact points in said upper metallization structure is larger than the number of said electrical contact points of said interconnecting metallization structure, by a substantial amount.

14. The structure of claim 1 wherein said upper metallization system is formed to provide relocation capability, wherein electrical contact points in a top layer of said upper metallization system are connected to electrical contact points in said interconnecting metallization structure, wherein said relocation capability is provided by providing said electrical contact points in said top layer of said upper metallization system in s different sequence than said electrical contact points in said interconnecting metallization structure.

15. The structure of claim 1 wherein said upper metallization structure is formed to provide reduction capability, wherein electrical contact points in a top layer of said upper metallization structure are connected to electrical contact points, which are functionally equivalent to each other, in said interconnecting metallization structure, whereby the number of said electrical contact points in said upper metallization structure is less than the number of electrical contact points in said interconnecting metallization structure.

16. The structure of claim 3 wherein said insulating layers in said upper metallization structure comprise an organic material, wherein said insulating layers are thicker than intermetal dielectric layers in said interconnecting metallization structure.

17. The structure of claim 16 wherein said intermetal dielectric layers in said interconnecting metallization structure for formed of an inorganic material.

18. The structure of claim 1 wherein openings between said upper metal lines are wider than openings formed between said lower metal lines.

19. The structure of claim 1 wherein said top metallization structure provides a means to standardize next level packaging.

20. The structure of claim 19 wherein said next level packaging is Ball Grid Array (BGA) packaging.

21. The structure of claim 1 wherein said top metallization structure provides a means to simplify next level packaging.

22. The structure of claim 1 further comprising solder balls on pads on a top layer of said top metallization structure, for connection to next level packaging.

23. The structure of claim 1 further comprising wires bonded to pads on a top layer of said top metallization structure, for connection to next level packaging.

24. A semiconductor device structure comprising:

a semiconductor substrate having semiconductor devices formed thereon;

an interconnecting metallization structure comprising lower metal lines, formed over and connected to said devices;

electrical contact points on an upper surface of said interconnecting metallization structure and connected to said interconnecting metallization structure;

a passivation layer deposited over said interconnecting metallization structure and over said electrical contact points;

openings through said passivation layer, exposing said electrical contact points; and

an upper metallization structure within said openings and over said passivation layer, comprising upper metal lines, connected to said interconnecting metallization structure, wherein said upper metal lines are substantially wider than said lower metal lines.

25. A semiconductor device structure comprising:

a semiconductor substrate having semiconductor devices formed thereon;

an interconnecting metallization structure comprising lower metal lines in layers, separated by inorganic intermetal dielectric layers, formed over and connected to said devices;

electrical contact points on an upper surface of said interconnecting metallization structure and connected to said interconnecting metallization structure;

a passivation layer deposited over said interconnecting metallization structure and over said electrical contact points;

openings through said passivation layer, exposing said electrical contact points; and

an upper metallization structure within said openings and over said passivation layer, comprising upper metal lines, separated by organic dielectric layers, connected to said interconnecting metallization structure, wherein said organic dielectric layers are thicker than said inorganic intermetal dielectric layers.