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Top layers of metal for high performance IC's

  • US 6,657,310 B2
  • Filed: 10/09/2001
  • Issued: 12/02/2003
  • Est. Priority Date: 12/21/1998
  • Status: Expired due to Term
First Claim
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1. A semiconductor device structure comprising:

  • a semiconductor substrate having semiconductor devices formed thereon;

    an interconnecting metallization structure comprising lower metal lines, formed over and connected to said devices;

    electrical contact points on an upper surface of said interconnecting metallization structure and connected to said interconnecting metallization structure;

    a passivation layer deposited over said interconnecting metallization structure and over said electrical contact points;

    openings through said passivation layer, exposing said electrical contact points; and

    an upper metallization structure within said openings and over said passivation layer, comprising upper metal lines, connected to said interconnecting metallization structure, wherein said upper metal lines are substantially thicker than said lower metal lines.

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