Multi-layered inductance element

• US 6,657,530 B2
• Filed: 06/06/2002
• Issued: 12/02/2003
• Est. Priority Date: 12/14/2001
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yamagata, Kousaku
• Primary Examiner(s): MAI, ANH T
• Application Number:
  US10/162,635
• Publication Number:
  US 20030112115A1
• Time in Patent Office: 544 Days
• Field of Search: 336/200, 336/223, 336/232, 296/021
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 41/045 Trimming
• CPC Class Codes: H05K 1/165 incorporating printed inductors
• CPC Class Codes: H05K 2201/0715 provided by an outer layer of PCB
• CPC Class Codes: H05K 2201/09536 Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/097 Alternating conductors, e.g. alternating different shaped pads, twisted pairs; Alternating components

Abstract

On each surface of a dielectric substrate, arranged are a first conductor line pattern having a plurality of first line segments and a second conductor line pattern having a plurality of second line segments. Ends of each first conductor line segment overlap the second conductor line segments, and the first and second line segments are connected via through-holes, thereby forming a single spiral conductor line. Each second conductor line segment for connecting adjacent first conductor line segments has a pair of end parts connected to the first conductor line segments via through-holes and a halfway part having a smaller width.

Claims

1. A multi-layered inductance element comprising:

at least one dielectric substrate having a first and second surfaces;

a first conductor line pattern including a plurality of first conductor line segments being apart from each other and disposed on the first surface of the dielectric substrate, wherein the first conductor line segments exhibit a substantially looped configuration as a whole if adjacent first conductor line segments are connected with each other;

a second conductor line pattern including a plurality of second conductor line segments being apart from each other and disposed on the second surface of the dielectric substrate, wherein the second conductor line segments exhibit a substantially looped configuration as a whole if adjacent second conductor line segments are connected with each other; and

a plurality of through-holes penetrating through the dielectric substrate, each through-hole electrically connecting one end of one of the first conductor line segments and one end of one of the second conductor line segments,

wherein each of the first conductor line segments extends over at least a part of one of the second conductor line segments, the plurality of first conductor line segments being connected with the plurality of second conductor line segments via the through-holes, thereby forming a spiral conductor line in which a direction of current flow in the first conductor line pattern is the same as that in the second conductor line pattern,

and wherein each of the second conductor line segments includes a pair of end parts and a halfway part having a width which is smaller than that of the end parts, the end parts being connected to adjacent first conductor line segments via the through-holes.

2. The multi-layered inductance element as recited in claim 1, wherein the first conductor line pattern contains at least two gaps where adjacent first conductor line segments are spaced apart, two second conductor line segments being disposed over the two gaps, respectively, and wherein one of the second conductor line segments over one of the gaps for connecting two adjacent first conductor line segments is angled at 90 degrees with the other of the second conductor line segments over the other of the gaps for connecting two adjacent first conductor line segments.

3. The multi-layered inductance element as recited in claim 2, wherein the first conductor line pattern contains at least four gaps where adjacent first conductor line segments are spaced apart, four second conductor line segments being disposed over the four gaps, and wherein two of the second conductor line segments over two of the gaps for connecting adjacent first conductor line segments are angled at 90 degrees with the other two of the second conductor line segments over the other two of the gaps for connecting adjacent first conductor line segments.