Unified memory distributed across multiple nodes in a computer graphics system

• US 6,657,632 B2
• Filed: 01/24/2001
• Issued: 12/02/2003
• Est. Priority Date: 01/24/2001
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Alcorn, Byron A, Emmot, Darel N
• Primary Examiner(s): Bella, Matthew C.
• Assistant Examiner(s): Monestime, Mackly
• Application Number:
  US09/768,664
• Publication Number:
  US 20020145609A1
• Time in Patent Office: 1,042 Days
• Field of Search: 345/502, 345/503, 345/504, 345/505, 345/506, 345/542, 345/557, 711/118, 711/130, 711/141, 711/147, 711/152, 712/10, 712/11, 712/16, 712/23, 712/28, 712/31
• US Class Current: 345/502
• CPC Class Codes: G06F 2209/509 Offload
• CPC Class Codes: G09G 2360/12 Frame memory handling
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.

Claims

1. A system of integrated circuit components defining a plurality of nodes and a random access memory (RAM) connected to each node, each node comprising:

at least one functional unit configured to carry out a predetermined processing function;

a communication mechanism configured to manage and control communication of information with other nodes;

a memory controller configured to control writes to and reads from the RAM connected to the node;

control means for controlling the use and access of memory storage by remote functional units, and wherein the RAM is segmented to include at least one segment dedicated to the control means of the connected node, at least one additional segment dedicated to carrying out a functional operation of the system, and at least one additional segment dedicated to a portion of a texture map surface and a portion of an image surface, and a remaining texture map surface and image surface are stored in memory segments of RAMs connected to other nodes, wherein various texture map surface segments and image surface segments are partitioned and stored among the RAMs in a non-duplicative manner; and

wherein the system is further configured to permit read access to a RAM by a plurality of the nodes in the system, but is further configured to limit write access to a RAM to only the node to which the RAM is connected.

2. The system of claim 1, wherein the system is a computer graphics system.

3. The system of claim 1, wherein the at least one functional unit is one selected from the group consisting of a texture mapping component, a geometry accelerator, a shader, a z/blend component, a rasterizer, a tiler, and a cache controller.

4. The system of claim 1, wherein the control means includes a memory segment containing at least one work queue, the work queue being in the form of a first-in-first-out instruction queue for the at least one functional unit.

5. The system of claim 4, wherein the work queue contains a plurality of messages.

6. The system of claim 5, wherein messages may be communicated between different nodes under control of the control means.

7. The system of claim 1, wherein the plurality of nodes are interconnected via a plurality of serial communication links.