Circuit for optimizing power consumption and performance

• US 6,657,912 B1
• Filed: 03/20/2003
• Issued: 12/02/2003
• Est. Priority Date: 03/20/2003
• Status: Expired due to Fees

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Rohatgi, Nishith, Correale, Anthony Jr.
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US10/393,286
• Time in Patent Office: 257 Days
• Field of Search: 365/189.04, 365/227
• US Class Current: 365/227
• CPC Class Codes: G11C 2207/007 Register arrays
• CPC Class Codes: G11C 2207/2281 Timing of a read operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A memory bit line multiplexor circuit is disclosed. The circuit comprises at least one memory cell arrangement. The circuit includes a first active device coupled to the at least one memory cell arrangement and for coupling a first node to a second node within the circuit. The first active device is controlled by a write through read (!wtr) signal. The circuit includes a second active device coupled to the second node and a gate. The gate has a first input coupled to the first node; a second input coupled to the !WTR signal, and a third input being controlled by an inversion of the output of the circuit. The gate and the second active device provide a pulsed self-timed response that minimizes power consumption while optimizing performance of the circuit. A circuit in accordance with the present invention is disclosed in which the most power, and area efficient realizations can be employed for applications requiring broad power supply operating ranges. The circuit employs a simple logic gate system configured to create a self-timed pulsed stimulus for allowing improved performance over a very broad Vdd operation range while simultaneously reducing power.

Claims

1. A memory bit line multiplexor circuit comprising:

at least one memory cell arrangement;

a first active device coupled to the at least one memory cell arrangement for coupling a first node to a second node within the circuit;

the first active device being controlled by a write through read (!wtr) signal;

a second active device coupled to the second node; and

a gate;

the gate having a first input coupled to the first node;

a second input coupled to the !WTR signal, and a third input being controlled by an inversion of the output of the circuit;

wherein the gate and the second active device provide a pulsed self-timed response that minimizes power consumption while optimizing performance of the circuit.

2. The memory bit line multiplexor circuit of claim 1 wherein the first active device comprises a nfet device and the second active device comprises a pfet device.

3. The memory bit line multiplexor circuit of claim 1 wherein the gate comprises a 3-input NAND gate.

4. The memory bit line multiplexor circuit of claim 1 wherein the at least one memory cell arrangement comprises a plurality of memory cell arrangements.

5. The memory bit line multiplexor circuit of claim 4 wherein each of the memory cell arrangements comprise;

a memory cell; and

a third active device coupled to memory cell for receiving a word line driver (WLn) signal, the WLn signal for transferring the content from the memory cell to the first node.

6. The memory bit line multiplexor circuit of claim 5 that includes a n/p pair transmission gate coupled to the second node.

7. The memory bit line multiplexor circuit of claim 6 that includes a feedback active device coupled between the inversion of the output of the circuit and the second node.

8. The memory bit line multiplexor circuit of claim 1 which includes an inverter system coupled to the output.

9. The memory bit line multiplexor circuit of claim 8 wherein the inverter system includes:

a first inverter, an input of the first inverter coupled to the second node; and

a second inverter, an input of second inverter coupled to an output of the first inverter; and

for providing the output of the circuit.

14. The memory bit line multiplexor circuit of claim 1 wherein the gate comprises a 3-input NAND gate.

10. A memory bit line multiplexor circuit comprising:

at least one memory cell arrangement;

a first active device coupled to the at least one memory cell arrangement for coupling a first node to a second node within the circuit;

the first active device being controlled by a write through read (!wtr) signal;

a second active device coupled to the second node;

a gate;

the gate having a first input coupled to the first node;

a second input coupled to the !WTR signal, and a third input for controlling an output of the circuit;

wherein the gate and the second active device provide a pulsed self-timed response that minimizes power consumption while optimizing performance of the circuit;

a n/p pair transmission gate coupled to the second node; and

a feedback active device coupled between the inversion of the output of the circuit and the second node.

11. The memory bit line multiplexor circuit of claim 10 wherein each of the memory cell arrangements comprise;

a memory cell; and

a third active device coupled to memory cell for receiving a word line driver (WLn) signal, the WLn signal for transferring the content from the memory cell to the first node.

12. The memory bit line multiplexor circuit of claim 10 wherein the inverter system includes:

a first inverter, an input of the first inverter coupled to the second node; and

a second inverter, an input of second inverter coupled to an output of the first inverter; and

for providing the output of the circuit.

13. The memory bit line multiplexor circuit of claim 10 wherein the first active device comprises a nfet device and the second active device comprises a pfet device.