Method and apparatus for address translation on PCI bus over infiniband network

• US 6,658,521 B1
• Filed: 01/30/2001
• Issued: 12/02/2003
• Est. Priority Date: 12/22/2000
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Biran, Giora, Makhervaks, Vadim
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/772,376
• Time in Patent Office: 1,036 Days
• Field of Search: 710/300, 710/22, 710/26, 710/28, 710/36, 710/35, 710/107, 710/305, 710/306, 710/308, 710/310, 710/311, 710/313, 710/315, 709/212
• US Class Current: 710/315
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A system having a plurality of PCI devices, a PCI bus, a host system with a host memory, an network, and a target channel adpater. The plurality of PCI devices are attached to the PCI bus, which is connected via the target channel adpater and the network to the host system. The target channel adpater translates PCI bus transactions and PCI bus interrupts into network requests and network requests to PCI transactions. Each of the PCI devices has a PCI address range associated with it. A PCI memory window is allocated on the target channel adpater and is assigned to the host system. The PCI devices are enabled to post a pseudo address that belongs to the target channel adpater on the PCI bus when reading data via the network from the host memory or when writing data in the host memory via the network, the pseudo address comprising a base part (VABase) and an offset part (Offset). The base part (VABase) identifies the PCI memory window being assigned to the host system and the offset part (Offset) is useable for calculating a virtual address (VA) specifying a physical memory location in the host memory.

Claims

1. A method for enabling one or more PCI devices to read data via a network from a memory of a host system or to write data to said memory on said host system via said network, wherein said PCI devices are attached to a PCI bus and connected to said network via a target channel adpater that translates PCI bus transactions and interrupts into network requests and that translates network requests to PCI transactions, and wherein each of said PCI devices has a PCI address range associated therewith, comprising:

(a) allocating a PCI memory window on said target channel adpater, said PCI memory window being assigned to said host system,

(b) posting a pseudo address that belongs to said target channel adpater on said PCI bus when reading data via said network from said memory of said host system or when writing data on said memory of said host system via said network, wherein said pseudo address comprises a base part and an offset part,

(c) using said base part to identify said PCI memory window assigned to said host system by step (a), and

(d) using said offset part for calculating a virtual address specifying a physical location of said memory at said host system.

2. The method of claim 1, wherein said pseudo address posted on said PCI bus serves as an index to said PCI memory window assigned to said host system.

3. The method of claim 1, wherein said pseudo address posted on said PCI bus enables at least one of said PCI devices to fetch information from said PCI memory window assigned to said host system.

4. The method of claim 1, wherein said target channel adpater includes a PCI memory window table with a plurality of entries, each entry being associated with a base part of said pseudo address.

5. The method of claim 4, wherein said memory includes a plurality of memory regions, and wherein each entry in said PCI memory window table corresponds to a different one of said plurality of memory regions on said host system.

6. The method of claim 5, wherein said host system comprises a device driver for at least one of said PCI devices, and wherein said device driver registers said memory regions on said host system with said target channel adpater, thereby making said memory regions accessible by said at least one of said PCI devices.

7. The method of claim 6, wherein said host system further comprises means for enabling said device driver to register said memory regions on said host system.

8. The method of claim 4, wherein said host system further comprises means for creating and maintaining said PCI memory window table.

9. The method of claim 8, wherein said means for creating and maintaining also registers said memory region on said host system with appropriate permissions and allocates said PCI memory window on said target channel adpater.

10. A method for address translation between one or more PCI devices that are attached to a PCI bus and connected via a target channel adpater and an network to a host system, wherein each of said PCI devices has a PCI address range associated therewith, and wherein said target channel adpater translates PCI bus transactions and PCI bus interrupts into network requests and network requests to PCI transactions, comprising:

(a) allocating a PCI memory window on said target channel adpater, said PCI memory window being assigned to said host system,

(b) posting a pseudo address that belongs to said target channel adpater on said PCI bus, wherein said pseudo address comprises a base part and an offset part,

(c) using said base part to identify said PCI memory window assigned to said host system by step (a), and

(d) using said offset part for calculating a virtual address specifying a physical location of a memory of said host system.

11. The method of claim 10, wherein said pseudo address posted on said PCI bus serves as an index to said PCI memory window assigned to said host system.

12. The method of claim 10, wherein said pseudo address posted on said PCI bus enables at least one of said PCI devices to fetch information from said PCI memory window assigned to said host system.

13. The method of claim 10, wherein said target channel adpater includes a PCI memory window table with a plurality of entries, each entry being associated with a base part of said pseudo address.

14. The method of claim 13, wherein said memory includes a plurality of memory regions, and wherein each entry in said PCI memory window table corresponds to a different one of said plurality of memory regions on said host system.

15. The method of claim 14, wherein said host system comprises a device driver for at least one of said PCI devices, and wherein said device driver registers said memory regions on said host system with said target channel adpater, thereby making said memory regions accessible by said at least one of said PCI devices.

16. The method of claim 15, wherein said host system further comprises means for enabling said device driver to register said memory regions on said host system.

17. The method of claim 16, wherein said means for creating and maintaining also registers said memory regions on said host system with appropriate permissions and allocates said PCI memory window on said target channel adpater.

18. The method of claim 13, wherein said host system further comprises means for creating and maintaining said PCI memory window table.

19. A system comprising:

a host system that includes a host memory,

a network that carries a plurality of network requests,

a PCI bus that carries a plurality of PCI bus transactions and/or PCI bus interrupts,

a target channel adapter that connects said PCI bus via said network to said host system and that translates said PCI bus transactions and PCI bus interrupts, which are destined for said host system, to network requests and said network requests, which are destined for said PCI bus, to said PCI bus transactions, wherein a PCI memory window is allocated on said target channel adpater and is assigned to said host system, and

one or more PCI devices that are attached to said PCI bus, that each have a PCI address range associated therewith and that each, when enabled, posts on said PCI bus one of said plurality of PCI bus transactions or PCI bus interrupts that includes a pseudo address, which belongs to said target channel adpater, when reading data via said network from said host memory or when writing data in said host memory via said network, wherein said pseudo address comprises a base part and an offset part, wherein said base part identifies said PCI memory window and wherein said offset part is useable for calculating a virtual address specifying a physical memory location in said host memory.

20. The system of claim 19, wherein said PCI devices are legacy PCI devices.

21. The system of claim 19, wherein a plurality of said PCI devices are combined to form an input/output unit.

22. The system of claim 19, wherein said target channel adpater comprises a PCI memory window table with a pluralty of entries, each entry being associated with a base part of said pseudo address.

23. The system of claim 19, wherein said host memory includes a plurality of memory regions, and wherein said host system comprises a device driver for at least one of said PCI devices, and wherein said device driver is enabled to register said memory regions of said host memory with said target channel adpater for making said memory regions accessible by said at least one of said PCI devices.

24. The system of claim 19, further comprising software means for execution of a pseudo address generation algorithm, wherein said pseudo address generation algorithm generates said pseudo address.

25. The system of claim 19, further comprising software means for execution of a virtual address calculation algorithm, wherein said virtual address calculation algorithm calculates said virtual address.

26. A memory media for a target channel adapter that is interconnected with one or more PCI devices via a PCI bus and connected via an network to a host system, wherein each of said PCI devices has a PCI address range associated therewith, and wherein said target channel adpater translates PCI bus transactions and PCI bus interrupts into network requests and network requests to PCI transactions, comprising:

first means for causing said target channel adapter to process an allocated PCI memory window, said PCI memory window being assigned to said host system,

second means for causing said target channel adapter to post a pseudo address that belongs to said target channel adpater on said PCI bus, wherein said pseudo address comprises a base part and an offset part,

third means for causing said target channel adapter to use said base part to identify said PCI memory window assigned to said host system by said first means, and

fourth means for causing said target channel adapter to use said offset part for calculating a virtual address specifying a physical location of a memory of said host system.

27. The memory media of claim 26, wherein said pseudo address posted on said PCI bus serves as an index to said PCI memory window assigned to said host system.

28. The memory media of claim 26, wherein said pseudo address posted on said PCI bus enables at least one of said PCI devices to fetch information from said PCI memory window assigned to said host system.

29. The memory media of claim 26, further comprising fifth means for causing said target channel adapter to process a PCI memory window table with a plurality of entries, each entry being associated with a base part of said pseudo address.

30. The memory media of claim 29, wherein said memory includes a plurality of memory regions, and wherein each entry in said PCI memory window table corresponds to a different one of said plurality of memory regions on said host system.

31. A system comprising:

a host system that includes a host memory, a network and a PCI bus,

a target channel adapter that connects said PCI bus via said network to said host system, wherein a PCI memory window is allocated on said target channel adpater and is assigned to said host system, and

one or more PCI devices that are attached to said PCI bus that each, when enabled, posts on said PCI bus a pseudo address, which belongs to said target channel adpater, when reading data via said network from said host memory or when writing data in said host memory via said network, wherein said pseudo address comprises a base part and an offset part, wherein said base part identifies said PCI memory window and wherein said offset part is indicative of a virtual address that specifies a physical memory location in said host memory.