Method and apparatus for write cache flush and fill mechanisms

• US 6,658,533 B1
• Filed: 09/21/2000
• Issued: 12/02/2003
• Est. Priority Date: 09/21/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bogin, Zohar, Clohset, Steven J.
• Primary Examiner(s): MCLEAN MAYO, KIMBERLY N
• Application Number:
  US09/667,405
• Time in Patent Office: 1,167 Days
• Field of Search: 711/133, 711/135, 711/134, 711/136, 711/118, 711/147, 711/146
• US Class Current: 711/135
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/304 In main memory subsystem

Abstract

A write cache that reduces the number of memory accesses required to write data to main memory. When a memory write request is executed, the request not only updates the relevant location in cache memory, but the request is also directed to updating the corresponding location in main memory. A separate write cache is dedicated to temporarily holding multiple write requests so that they can be organized for more efficient transmission to memory in burst transfers. In one embodiment, all writes within a predefined range of addresses can be written to memory as a group. In another embodiment, entries are held in the write cache until a minimum number of entries are available for writing to memory, and a least-recently-used mechanism can be used to decide which entries to transmit first. In yet another embodiment, partial writes are merged into a single cache line, to be written to memory in a single burst transmission.

Claims

1. An apparatus, comprising:

writecache storage to store cache lines of write data received from a cache tobe written to memory;

a flush dispatcher coupled to the write cache storage to dispatch the cache lines to the memory;

control logic to

dispatch at least one of the cache lines to the memory if a number of cache lines in the write cache storage exceeds a first predetermined value representing less than a full write cache storage;

not dispatch any of the cache lines to the memory if the number of cache lines in the write cache storage does not exceed the first predetermined value;

dispatch the at least one of the cache lines with a high priority if the number of cache lines in the write cache storage exceeds a second predetermined value higher than the first predetermined value; and

dispatch the at least one of the cache lines with a low priority if the number of cache lines in the write cache storage does not exceed the second predetermined value.

2. The apparatus of claim 1, wherein the control logic is further to dispatch an oldest one of the cache lines first if the number of cache lines in the write cache storage exceeds the first predetermined value.

3. A method, comprising:

receiving cache lines of write data from a cache;

storing the cache lines of write data in write cache storage;

dispatching at least one of the cache lines to memory if a number of cache lines in the write cache storage exceeds a first predetermined value representing less than a full write cache storage;

not dispatching any of the cache lines to the memory if the number of cache lines in the write cache storage does not exceed the first predetermined value;

dispatching the at least one of the cache lines with a high priority if the number of cache lines in the write cache storage exceeds a second predetermined value higher than the first predetermined value; and

dispatching the at least one of the cache lines with a low priority if the number of cache lines in the write cache storage does not exceed the second predetermined value.

4. The method of claim 3, wherein said dispatching further includes dispatching an oldest one of the cache lines first if the number of cache lines in the write cache storage exceeds the first predetermined value.

5. A machine-readable medium having stored thereon instructions, which when executed by a processor cause said processor to perform:

receiving cache lines of write data from a cache;

storing the cache lines of write data in write cache storage;

dispatching at least one of the cache lines to memory if a number of cache lines in the write cache storage exceeds a first predetermined value representing less than a full write cache storage; and

not dispatching any of the cache lines to the memory if the number of cache lines in the write cache storage does not exceed the first predetermined value;

dispatching the at least one of the cache lines with a high priority if the number of cache lines in the write cache storage exceeds a second predetermined value higher than the first predetermined value; and

dispatching the at least one of the cache lines with a low priority if the number of cache lines in the write cache storage does not exceed the second predetermined value.

6. The medium of claim 5, wherein said dispatching further includes dispatching an oldest one of the cache lines first if the number of cache lines in the write cache storage exceeds the first predetermined value.

7. An apparatus, comprising:

write cache storage to receive write requests to receive write data from a cache and to store cache lines of the write data in a memory;

a flush dispatcher coupled to the write cache storage to dispatch the cache lines to the memory;

control logic to

select a first cache line with a first address in the write cache storage for dispatching;

dispatch the first cache line to the memory if a number of cache lines in the write cache storage exceeds a first predetermined value representing less than a full write cache storage;

not dispatch any of the cache lines to the memory if the number of cache lines in the write cache storage does not exceed the first predetermined value;

determine if a second cache line in the write cache storage has a second address within a predetermined range of the first address;

dispatch the second cache line if the second address is within the predetermined range of the first address;

determine if a third cache line associated with a particular one of a plurality of partial write requests is stored in the write cache storage;

if the third cache line is not stored in the write cache storage retrieve the third cache line from the memory;

store the retrieved third cache line in the write cache storage; and

merge the particular one of the plurality of partial write requests into the retrieved third cache line;

dispatch the first cache line with a high priority if the number of cache lines in the write cache storage exceeds a second predetermined value higher than the first predetermined value; and

dispatch the first cache line with a low priority if the number of cache lines in the write cache storage exceeds the first predetermined value and does not exceed the second predetermined value.

8. The apparatus of claim 7, wherein the predetermined range is programmable.