Pipelined asynchronous processing

• US 6,658,550 B2
• Filed: 04/30/2002
• Issued: 12/02/2003
• Est. Priority Date: 07/16/1997
• Status: Expired due to Term

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Manohar, Rajit, Lines, Andrew, Cummings, Uri, Nystroem, Mika, Martin, Alain J.
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Levin, Naum B
• Application Number:
  US10/137,035
• Publication Number:
  US 20020156995A1
• Time in Patent Office: 581 Days
• Field of Search: 712/18, 712/23, 712/25, 712/33, 712/41, 712/203, 712/204, 712/207, 712/210, 712/216, 712/219, 712/228, 712/241, 712/244
• US Class Current: 712/23
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 15/8053 Vector processors
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers
• CPC Class Codes: G06F 9/3871 Asynchronous instruction pipeline, e.g. using handshake signals between stages

Abstract

An asynchronous processor having pipelined instruction fetching and execution to implement concurrent execution of instructions by two or more execution units. A writeback unit is connected to execution units and memory units to control information updates and to handle precise exception. A pipelined completion mechanism can be implemented to improve the throughput.

Claims

1. An asynchronous system for information processing which is independent of a clock signal, comprising:

a plurality of execution units including a program counter unit, a memory unit, and at least one arithmetic logic unit, said execution units connected relative to one another in parallel;

a register unit having registers, connected to said execution units;

a fetch unit, connected to said program counter unit to receive a program counter signal and configured to retrieve instructions from an instruction memory unit according to said program counter signal;

a decoder connected to receive said instructions from said fetch unit and configured to decode said instructions to generate decoded instructions, wherein said decoder is connected to communicate with each of said execution units and said register unit;

a writeback unit communicating with said execution units and register unit to filter and route information from one member of said execution units and register unit to another member;

a first queue disposed between said decoder and said writeback unit to store and transfer ordering information to said writeback unit to indicate an order in which said decoder dispatches said decoded instructions to said execution units; and

a second queue disposed between said program counter unit and said writeback unit to store and transfer said program counter signal to said writeback unit,

wherein said program counter unit, said fetch unit, said instruction memory unit, and said decoder form a pipelined fetching loop operable to simultaneously transfer at least two instructions unsynchronized with respect to each other.