Programmable built-in self-test system for semiconductor memory device

• US 6,658,611 B1
• Filed: 11/16/1999
• Issued: 12/02/2003
• Est. Priority Date: 11/19/1998
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jun, Hong-Shin
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US09/441,625
• Time in Patent Office: 1,477 Days
• Field of Search: 714/719, 714/718, 714/732-733, 365/201
• US Class Current: 714/719
• CPC Class Codes: G01R 31/31901 Analysis of tester Performance; Tester characterization
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines
• CPC Class Codes: G11C 29/50012 of timing

Abstract

A programmable built-in self-test (BIST) system comprises a parameter register file for storing parameters to test a memory device. The parameters are externally programmed depending upon characteristics of the memory device. The BIST system tests the memory device with optimum test patterns stored in the parameter register file. Thus, the memory device can be tested by the BIST system, flexibly, although the memory device has various reading/writing control methods and their complex timing. Further, the timing characteristics of the memory device can be tested in a developing step of a memory core. Therefore, a memory test efficiency and its error detection efficiency can be increased.

Claims

1. A built-in self-test (BIST) system for a semiconductor memory, comprising:

a parameter register file having a plurality of externally programmable registers, for storing parameters to test the memory;

a BIST machine for controlling read/write operations of the memory in response to the parameters stored in the parameter register file, sensing an occurrence of an error according to the read/write operations and producing error test results in the form of one or more signatures;

a multi-input signature register (MISR) for compressing test results from the BIST machine; and

a clock input circuit for receiving a first clock signal having a first frequency and for receiving a clock doubling selection signal, and for outputting a second clock signal to the BIST system and the memory so as to test the memory,

wherein the second clock signal has the first frequency when the clock doubling selection signal has a first value, and the second clock signal has a second frequency as a double of the first frequency, when the clock doubling selection signal has a second value.

2. The BIST system of claim 1, wherein the parameter register file comprises:

a command sequence register for storing a plurality of commands to test the memory;

a bank interleaving register for setting up whether or not a bank interleaving operation is applied to the memory test;

an up/down register for setting up an address scanning direction in the memory test;

an error location register for setting up whether or not an error location function to output an error information is performed in the memory test;

a pattern register for specifying a data background to write test data;

a refresh interval register for setting up a refresh interval of the memory; and

an address scanning register for determining an address scanning method for the memory test.

3. The BIST system of claim 2, wherein the BIST machine comprises:

a BIST controller for controlling overall operations of the BIST system so as to test the memory, in response to the parameters stored in the parameter register file;

a data generator for generating data to be written to the memory;

an address generator for generating read/write addresses of the memory;

a control signal generator for generating a plurality of control signals to control the read/write operations of the memory;

a comparator for comparing the data written in the memory with the data read from an address region corresponding to the written data so as to detect the error; and

an error analyzer for outputting an address corresponding to the detected error and an error bit information when the error is detected by the comparator.

4. The BIST system of claim 3, wherein the plural registers included in the parameter register file are connected in series to compose a first scan chain, and the data generator, address generator, the control signal generator, the comparator and the error analyzer are coupled in series to compose a second scan chain,

wherein the first scan chain and the second scan chain compose a third scan chain by coupling with each other.

5. The BIST system of claim 4, which further comprises:

a simple mode for testing the whole memory area, and outputting test results compressed by the MISR;

a setup mode for loading the parameters into the parameter register file from a source external to the memory;

a run mode for testing the memory by the parameters from the parameter register file; and

a scan mode for testing the BIST system itself.

6. The BIST system of claim 5, which further comprises a multiplexer for outputting at least one of test results from the BIST machine, the MISR, or the parameter register file, selectively.