Developement of hardmac technology files (CLF, tech and synlib) for RTL and full gate level netlists

• US 6,658,628 B1
• Filed: 12/19/2001
• Issued: 12/02/2003
• Est. Priority Date: 12/19/2001
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Porter, Michael, Lindberg, Peter F., Landy, Robert E., Lang, Craig R.
• Primary Examiner(s): Garbowski, Leigh M.
• Application Number:
  US10/025,123
• Time in Patent Office: 713 Days
• Field of Search: 716/1-21
• US Class Current: 716/103
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A method for generating one or more hardmacro technology files comprising the steps of determining a netlist, generating a timing constraints file in response to (i) the netlist and (ii) a time budget, and generating the hardmacro technology files in response to (i) the netlist and (ii) the timing constraints file.

Claims

1. A method for generating one or more hardmacro technology files comprising the steps of:

(A) determining a netlist;

(B) generating a timing constraints file in response to (i) said netlist and (ii) a time budget; and

(C) generating said hardmacro technology files in response to (i) said netlist and (ii) said timing constraints file.

2. The method according to claim 1, wherein:

said netlist is selected from the group consisting of (i) register-transfer-level (RTL) netlists, (ii) skeleton netlists, (iii) empty module netlists, and (iv) Verilog stub files of individual hierarchical hardmacros (HHMs); and

said one or more hardmacro technology files are selected from the group consisting of hardmacro technology files generated in a format having a suffix (i) .clf and (ii) .tech.

3. The method according to claim 1, wherein:

said netlist is configured as a full gate netlist; and

said one or more hardmacro technology files are selected from the group consisting of hardmacro technology files generated in a format having a suffix (i) .clf, (ii) .tech, and (iii) .synlib.

4. The method according to claim 3, wherein step (B) further comprises generating said timing constraints file in response to (i) one or more delay files and (ii) a timing script file.

5. The method according to claim 4, wherein said one or more delay files comprise standard delay format (SDF) files.

6. The method according to claim 4, wherein step (B) further comprises generating said one or more delay files in response to (i) said netlist and (ii) one or more extracted parasitics.

7. The method according to claim 4, wherein step (B) further comprises generating said timing constraints file to a predetermined level of accuracy.

8. The method according to claim 3, wherein step (B) further comprises generating one or more name map files in response to said netlist.

9. The method according to claim 8, wherein step (C) further comprises generating said one or more hardmacro technology files in response to said one or more name map files.

10. The method according to claim 3, wherein step (B) further comprises generating one or more (i) input side timing delays, (ii) internal delays, and (iii) output side timing delays.

11. The method according to claim 3, wherein step (C) further comprises generating a clock timing file.

12. The method according to claim 11, wherein step (B) comprises the sub-steps of:

(a) deleting any pre-existing timing constraints file;

(b) invoking a timing analysis tool;

(c) loading and linking said netlist; and

(d) loading said time budget.

13. The method according to claim 1, wherein step (B) further comprises generating (i) a worst case timing file, (ii) a best case timing file, and (iii) a test timing file.

14. The method according to claim 1, wherein said method further comprises the step of translating one or more source languages to one or more destination languages.

15. The method according to claim 1, wherein step (C) further comprises presenting said one or more hardmacro technology file to one or more analysis tools.

16. The method according to claim 15, wherein said analysis tools are selected from the group consisting of Avant! Corporation Avant!, LSI Logic Corporation MPS, LSI Logic Corporation MRS, Celestry Clockwise, Cadence Design Systems, Inc. Physically Knowledgeable Synthesis (PKS), and Synopsys Physical Compiler.

17. The method according to claim 1, wherein step (C) further comprises generating said one or more hardmacro technology files in response to one or more technology library files.

18. The method according to claim 1, wherein said method is configured to provide (i) accurate die size estimates, (ii) accurate prediction of repeater insertion into a layout, (iii) transportable syntax, and (iv) accurate delay and slack calculation.

19. A computer medium containing one or more sets of computer executable instructions for performing steps to generate one or more hardmacro technology files, wherein said steps comprise:

(A) determining a netlist;

(B) generating a timing constraints file in response to (i) said netlist and (ii) a time budget; and

(C) generating said hardmacro technology files in response to (i) said netlist and (ii) said timing constraints file.

20. An apparatus containing one or more sets of computer executable instructions for performing steps to generate one or more hardmacro technology files, wherein said steps comprise:

(A) determining a netlist;

(B) generating a timing constraints file in response to (i) said netlist and (ii) a time budget; and

(C) generating said hardmacro technology files in response to (i) said netlist and (ii) said timing constraints file.