Automated system-on-chip integrated circuit design verification system

• US 6,658,633 B2
• Filed: 10/03/2001
• Issued: 12/02/2003
• Est. Priority Date: 10/03/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Robinson, James R., Devins, Robert J.
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US09/969,675
• Publication Number:
  US 20030093764A1
• Time in Patent Office: 790 Days
• Field of Search: 716/1-21, 702/118, 703/14, 710/5, 712/25, 714/33, 717/109, 717/110
• US Class Current: 716/106
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

Disclosed is a method of verifying the design of an integrated circuit chip comprised of one or more cores, comprising: creating a project core catalog comprising driver description files and application description files for each core; creating a system definition file for the integrated circuit chip; inputting the driver description files, the application description files and the system definition files into a code generator, the code generator outputting a test operating system test code; and applying the test operating system test code to a software simulation of the integrated circuit chip to perform design verification.

Claims

1. A method of verifying the design of an integrated circuit chip comprised of one or more cores, comprising:

creating a project core catalog comprising driver description files and application description files for each core;

creating a system definition file for said integrated circuit chip;

inputting said driver description files, said application description files and said system definition files into a code generator, said code generator outputting a test operating system test code; and

applying said test operating system test code to a software simulation of said integrated circuit chip to perform design verification.

2. The method of claim 1, wherein said driver description files and application description files are non-integrated circuit specific and said system definition file and said test operating system test code are integrated circuit specific.

3. The method of claim 1, further including the step of modifying one or more of said driver description files, said application description files and said system definition files in response to results of said design verification.

4. The method of claim 1, further including:

generating off chip driver description files and off chip application description files for off chip cores; and

including said off chip cores and an external memory mapped test device in said system definition file.

5. The method of claim 1, further including the step of selecting driver definition files and application definition files from said project core catalog to be inputted into said code generator based on a set of cores comprising said integrated circuit chip.

6. The method of claim 1, wherein said driver definition files includes code supporting one or more operations selected from the group consisting of declaring functions the driver will support, installing interrupts, declaring symbols and values for registers in the drivers core and defining displayable print strings.

7. The method of claim 1, wherein said application definition file includes code supporting one or more operations selected from the group consisting of declaring driver devices, declaring testcases for test applications, declaring test application callbacks and defining displayable print strings.

8. The method of claim 1, wherein said system definition file includes code supporting one or more operations selected from the group consisting of declaring and configuring test applications, declaring and configuring drivers, declaring external memory-mapped test device symbols and assignments, declaring and configuring memory regions, declaring mutexes, declaring registers, declaring exerciser strings, creation of testcases, declaring testcases, and specifying status of multiple instances of the same test application.

9. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for verifying the design of an integrated circuit chip comprised of one or more cores said method steps comprising:

creating a project core catalog comprising driver description files and application description files for each core;

creating a system definition file for said integrated circuit chip;

inputting said driver description files, said application description files and said system definition files into a code generator, said code generator outputting a test operating system test code; and

applying said test operating system test code to a software simulation of said integrated circuit chip to perform design verification.

10. The program storage device of claim 9, wherein said driver description files and application description files are non-integrated circuit specific and said system definition file and said test operating system test code are integrated circuit specific.

11. The program storage device of claim 9, further including the step of modifying one or more of said driver description files, said application description files and said system definition files in response to results of said design verification.

12. The program storage device of claim 9, further including:

generating off chip driver description files and off chip application description files for off chip cores; and

including said off chip cores and an external memory mapped test device in said system definition tile.

13. The program storage device of claim 9, further including the step of selecting driver definition files and application definition files from said project core catalog to be inputted into said code generator based on a set of cores comprising said integrated circuit chip.

14. The program storage device of claim 9, wherein said driver definition files includes code supporting one or more operations selected from the group consisting of declaring functions the driver will support, installing interrupts, declaring symbols and values for registers in the drivers core and defining displayable print strings.

15. The program storage device of claim 9, wherein said application definition file includes code supporting one or more operations selected from the group consisting of declaring driver devices, declaring testcases for test applications, declaring test application callbacks and defining displayable print strings.

16. The program storage device of claim 9, wherein said system definition file includes code supporting one or more operations selected from the group consisting of declaring and configuring test applications, declaring and configuring drivers, declaring external memory-mapped test device symbols and assignments, declaring and configuring memory regions, declaring mutexes, declaring registers, declaring exerciser strings, creation of testcases, declaring testcases, and specifying status of multiple instances of the same test application.

17. A computer system comprising a processor, an address/data bus coupled to said processor, and a computer-readable memory unit coupled to communicate with said processor, said memory unit containing instructions that when executed implement a method for verifying the design of an integrated circuit chip comprised of one or more cores, said method comprising the computer implemented steps of:

creating a project core catalog comprising driver description files and application description files for each core;

creating a system definition file for said integrated circuit chip;

inputting said driver description files, said application description files and said system definition files into a code generator, said code generator outputting a test operating system test code; and

applying said test operating system test code to a software simulation of said integrated circuit chip to perform design verification.

18. The computer system of claim 17, wherein said driver description files and application description files are non-integrated circuit specific and said system definition file and said test operating system test code are integrated circuit specific.

19. The computer system of claim 17, further including the step of modifying one or more of said driver description files, said application description files and said system definition files in response to results of said design verification.

20. The computer system of claim 17, further including:

generating off chip driver description files and off chip application description files for off chip cores; and

including said off chip cores and an external memory mapped test device in said system definition file.

21. The computer system of claim 17, further including the step of selecting driver definition files and application definition files from said project core catalog to be inputted into said code generator based on a set of cores comprising said integrated circuit chip.

22. The computer system of claim 17, wherein said driver definition files includes code supporting one or more operations selected from the group consisting of declaring functions the driver will support, installing interrupts, declaring symbols and values for registers in the drivers core and defining displayable print strings.

23. The computer system of claim 17, wherein said application definition file includes code supporting one or more operations selected from the group consisting of declaring driver devices, declaring testcases for test applications, declaring test application callbacks and defining displayable print strings.

24. The computer system of claim 17, wherein said system definition file includes code supporting one or more operations selected from the group consisting of declaring and configuring test applications, declaring and configuring drivers, declaring external memory-mapped test device symbols and assignments, declaring and configuring memory regions, declaring mutexes, declaring registers, declaring exerciser strings, creation of testcases, declaring testcases, and specifying status of multiple instances of the same test application.