Cross function block partitioning and placement of a circuit design onto reconfigurable logic devices

• US 6,658,636 B2
• Filed: 07/09/2001
• Issued: 12/02/2003
• Est. Priority Date: 07/09/2001
• Status: Expired due to Term

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Hochapfel, Eric G. F.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/901,780
• Publication Number:
  US 20030009735A1
• Time in Patent Office: 876 Days
• Field of Search: 716/1-21
• US Class Current: 716/117
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A first and a second netlist of a first and a second function block of a circuit design are correspondingly partitioned into at least a first and a second partition, and a third and a fourth partition respectively. The first and third partitions include majorities of the constituting elements of the first and second netlists respectively. The second and fourth partitions include minorities of the constituting elements of the first and second netlists. Placements of the constituting elements of the first and third partitions are correspondingly determined. The second and fourth partitions are merged to form a composite partition, which in turn is partitioned for joint determination of placement of these minority constituting elements of the first and second netlists of the first and second function blocks on logic devices. In one embodiment, the second and fourth partitions operate in the one clock domain, while the first and third partitions operate in one or more other clock domains.

Claims

1. A method comprising:

receiving a first and a second netlist of a first and a second function block of a circuit design;

correspondingly partitioning said first and second netlists of said first and second function blocks into at least a first and a second partition, and a third and a fourth partition respectively for correspondingly determining placement of constituting elements of said first and second netlists on logic devices, with the first partition having a majority of the constituting elements of said first netlist, the second partition having a minority of the constituting elements of said first netlist, the third partition having a majority of the constituting elements of said second netlist, and the fourth partition having a minority of the constituting elements of said second netlist;

merging said second and fourth partitions having minorities of the constituting elements of said first and second netlists to form a first composite partition of minority constituting elements of said first and second netlists of said first and second function blocks; and

partitioning said first composite partition for jointly determining placement of these minority constituting elements of said first and second netlists of said first and second function blocks on logic devices.

2. The method as set forth in claim 1, wherein the method further comprises correspondingly determining whether the amounts of constituting elements of said second and fourth partitions of minority constituting elements of said first and second netlists are below a first and a second threshold respectively, and said merging and said partitioning performed after said merging are conditionally performed only if the amounts of constituting elements of said second and fourth partitions of minority constituting elements of said first and second netlists are determined to be below said first and second thresholds respectively.

3. The method as set forth in claim 1, wherein the first and second thresholds are the same threshold.

4. The method as set forth in claim 1, wherein the constituting elements of the first partition are to operate in a first clock domain, the constituting elements of the third partition are to operate in a second clock domain, and the constituting elements of the second and fourth partitions are to operate in a common third clock domain.

5. The method as set forth in claim 4, wherein the first and second clock domains are the same clock domain.

6. The method as set forth in claim 1, wherein the method further comprises:

placing said constituting elements onto logic devices, including interconnecting elements of the logic devices employed to place said constituting elements.

7. The method as set forth in claim 1, wherein said logic devices are electrically reconfigurable logic devices.

8. The method as set forth in claim 7, wherein said electrically reconfigurable logic devices are field programmable gate arrays.

9. The method as set forth in claim 1, wherein

said partitioning of said first and second netlists further results in a fifth and a sixth partition of the constituting elements of the first and second netlists respectively, with said fifth partition also having a minority of the constituting elements of said first netlist and said sixth partition also having a minority of the constituting elements of said second netlist;

said merging further comprises merging said fifth and said sixth partitions having minorities of the constituting elements of the first and second netlists to form a second composite partition of minority constituting elements of the first and second netlists of the first and second function blocks; and

said partitioning performed after said merging further comprises partitioning said second composite partition of minority constituting elements of said first and second netlists of said first and second function blocks for jointly determining placement of these minority constituting elements of said first and second netlists of said first and second function blocks.

10. The method as set forth in claim 9, wherein the constituting elements of the first partition are to operate in a first clock domain, the constituting elements of the third partition are to operate in a second clock domain, the constituting elements of the second and fourth partitions are to operate in a common third clock domain, and the constituting elements of the second and fourth partitions are to operate in a common fourth clock domain.

11. An apparatus comprising:

storage medium having stored therein a plurality of programming instructions designed to operate the apparatus to;

receive a first and a second netlist of a first and a second function block of a circuit design,

correspondingly partition said first and second netlists of said first and second function blocks into at least a first and a second partition and a third and a fourth partition respectively for determining placement of constituting elements of said first and second netlists on logic devices, with the first partition having a majority of the constituting elements of said first netlist, the second partition having a minority of the constituting elements of said first netlist, the third partition having a majority of the constituting elements of said second netlist, and the fourth partition having a minority of the constituting elements of said second netlist,

merge said second and fourth partitions having minorities of the constituting elements of said first and second netlists to form a fifth partition of minority constituting elements of said first and second netlists of said first and second function blocks, and

partition said fifth partition for jointly determining placement of these minority constituting elements of said first and second netlists of said first and second function blocks on logic devices; and

one or more processors coupled to the storage medium to execute said programming instructions.

12. The apparatus as set forth in claim 11, wherein the programming instructions are further designed to operate the apparatus to correspondingly determine whether the amounts of constituting elements of said second and fourth partitions of minority constituting elements of said first and second netlists are below a first and a second threshold respectively, and to conditionally perform said merging and said partitioning performed after said merging only if the amounts of constituting elements of said second and fourth partitions of minority constituting elements of said first and second netlists are determined to be below said first and second thresholds respectively.

13. The apparatus as set forth in claim 11, wherein the first and second thresholds are the same threshold.

14. The apparatus as set forth in claim 11, wherein the constituting elements of the first partition are to operate in a first clock domain, the constituting elements of the third partition are to operate in a second clock domain, and the constituting elements of the second and fourth partitions are to operate in a common third clock domain.

15. The apparatus as set forth in claim 14, wherein the first and second clock domains are the same clock domain.

16. The apparatus as set forth in claim 11, wherein the programming instructions are further designed to operate the apparatus to place said constituting elements onto logic devices, including interconnecting elements of the logic devices employed to place said constituting elements.

17. The apparatus as set forth in claim 11, wherein said logic devices are electrically reconfigurable logic devices, and said apparatus further comprises said electrically reconfigurable logic devices.

18. The apparatus as set forth in claim 17, wherein said electrically reconfigurable logic devices are field programmable gate arrays.

19. The apparatus as set forth in claim 11, wherein

said partitioning of said first and second netlists further results in a fifth and a sixth partition of the constituting elements of the first and second netlists respectively, with said fifth partition also having a minority of the constituting elements of said first netlist and said sixth partition also having a minority of the constituting elements of said second netlist;

said programming instructions are further designed to operate the apparatus to further merge said fifth and said sixth partitions having minorities of the constituting elements of the first and second netlists to form a second composite partition of minority constituting elements of the first and second netlists of the first and second function blocks; and

said programming instructions are further designed to operate the apparatus to further partition said second composite partition of minority constituting elements of said first and second netlists of said first and second function blocks for jointly determining placement of these minority constituting elements of said first and second netlists of said first and second function blocks.

20. The apparatus as set forth in claim 19, wherein the constituting elements of the first partition are to operate in a first clock domain, the constituting elements of the third partition are to operate in a second clock domain, the constituting elements of the second and fourth partitions are to operate in a common third clock domain, and the constituting elements of the second and fourth partitions are to operate in a common fourth clock domain.

21. The apparatus as set forth in claim 11, wherein said apparatus is a selected one of a workstation and a networked server.