Method of making a chip carrier package using laser ablation

• US 6,660,559 B1
• Filed: 06/25/2001
• Issued: 12/09/2003
• Est. Priority Date: 06/25/2001
• Status: Expired due to Fees

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Sheridan, Richard P., Huemoeller, Ronald P.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Anya, Igwe U.
• Application Number:
  US09/888,950
• Time in Patent Office: 897 Days
• Field of Search: 438/106, 438/109, 438/113, 438/124, 438/126, 438/22, 438/118, 438/462, 438/597, 438/598, 438/612, 438/613, 438/678, 438/125, 438/162-167
• US Class Current: 438/106
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/485 Adaptation of interconnections, e.g. engineering charges, repair techniques
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/4848 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H05K 2203/107 Using laser light shaping a substrate by laser ablation H05K3/0026
• CPC Class Codes: H05K 2203/175 Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
• CPC Class Codes: H05K 3/0035 : of blind holes, i.e. having a metal layer at the bottom
• CPC Class Codes: H05K 3/0038 : combined with laser drilling through a metal layer
• CPC Class Codes: H05K 3/027 : the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
• CPC Class Codes: H05K 3/242 : characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
• CPC Class Codes: H05K 3/28 : Applying non-metallic protective coatings H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673

Abstract

A chip carrier package is made by using a laser-ablatable solder mask to cover areas of conductive traces on the surface of a substrate that were left uncovered during conventional processes using photoresist. These areas of the conductive traces are uncovered by using a laser to remove overlying portions of the solder mask. If a YAG laser is used, the conductive traces are removed at the same time the solder mask ablated. However, is a CO₂ laser is used, a conventional etching process removes the exposed portions of the traces after the solder mask is ablated.

Claims

1. A method for processing a substrate, comprising:

providing a substrate having at least one conductive layer;

forming a plurality of segments from the conductive layer, wherein a first plurality of the segments includes first portions for removal and second portions for plating;

depositing a solder mask over the first portions;

plating the second while the solder mask is overlying the first portions of the segments, and then removing at least portions of the solder mask overlying the first portions of the segments; and

removing the first portions of the segments, wherein the removing of at least potions of the solder mask and the removing of the first portions of the segments is accomplished with a single laser use.

2. The method of claim 1, wherein the plating comprises nickel plating or gold plating.

3. The method of claim 1, wherein the segments comprise bond fingers and designed-in shorts.

4. The method of claim 1, wherein the segments comprise copper.

5. The method of claim 1, wherein said solder mask is a photoimageable solder mask.

6. The method of claim 1, wherein said solder mask is a thermal solder mask.

7. A method of processing a substrate, comprising:

providing a multi-layer substrate having at least one conductive layer;

patterning traces from the conductive layer;

selecting a first portion from at least one of the traces, wherein the first portion is to be removed;

depositing a laser-ablatable mask over the first portion;

removing portions of the laser-ablatable mask overlying the first portion using a laser; and

removing the first portion completely using said laser, wherein the removing of the portions of the laser-ablatable mask and the removing of the first portion is accomplished with a single laser use.

8. The method of claim 7, further comprising plating at least one of the traces left exposed by the solder mask.

9. The method of claim 8, wherein the plating comprises nickel or gold plating.

10. The method of claim 7, wherein the traces comprise bond fingers and designed-in shorts and the first portion is part of the designed-in shorts.

11. The method of claim 7, wherein said laser-ablatable mask is a photoimageable mask.

12. The method of claim 7, wherein said laser-ablatable mask is a thermal mask.

13. A method for manufacturing a substrate, comprising:

providing a substrate having at least one conductive layer;

patterning bond fingers and designed-in shorts from the conductive layer, wherein the designed-in shorts comprise portions for removal;

depositing a solder mask over the portions of the designed-in shorts;

plating the bond fingers while the portions of the designed-in shorts are covered by the solder mask;

removing the solder mask overlying the portions of the designed-in shorts; and

removing the portions of the designed-in shorts, wherein the removing of the solder mask and the removing of the portions of the designed-in shorts is accomplished with a single laser use.

14. The method of claim 13, wherein said solder mask is a photoimageable solder mask.

15. The method of claim 13, wherein said solder mask is a thermal solder mask.

16. A method for processing a substrate, comprising:

providing a substrate having a plurality of metal traces, each said trace including a first portion and a second portion, wherein a thermal solder mask covers the first portion;

plating at least part of the second portion of the traces while using the solder mask to avoid plating the first portion, and then removing the solder mask from the first portion of the traces using a laser; and

removing the first portion of the traces, wherein the removing of the thermal solder mask and the underlying first portion of the traces is through a single laser operation.