Fabricating a DMOS transistor

• US 6,660,592 B2
• Filed: 05/29/2002
• Issued: 12/09/2003
• Est. Priority Date: 11/21/2001
• Status: Active Grant

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: Mosel Vitelic Incorporated
• Inventors: Chuang, Chiao-Shun, Tseng, Mao-Song, Chang, Chien-Ping, Ni, Cheng-Tsung
• Primary Examiner(s): Cao, Phat X.
• Assistant Examiner(s): Le, Thao X.
• Application Number:
  US10/160,299
• Publication Number:
  US 20030096485A1
• Time in Patent Office: 559 Days
• Field of Search: 438/270, 438/259, 438/242, 438/307, 257/330-338
• US Class Current: 438/270
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Embodiment of the present invention are directed to improving the performance of a DMOS transistor. A method of fabricating a DMOS transistor comprises providing a semiconductor substrate having a gate oxide and a trenched gate, and implanting first conductive dopants into a surface of the semiconductor substrate adjacent to the trenched gate to form a first doping region. An insulating layer is deposited over the semiconductor substrate; and selectively etching the insulating layer to form a source contact window over a central portion of the first doping region and to leave an insulator structure above the trenched gate. The source contact window of the insulating layer has an enlarged top portion which is larger in size than a bottom portion of the source contact window closer to the first doping region than the enlarged top portion. The enlarged top portion is typically bowl-shaped. Second conductive dopants are implanted through the source contact window to form a second doping region in the central portion of the first doping region.

Claims

1. A method of fabricating a DMOS transistor, the method comprising:

providing a semiconductor substrate having a gate oxide and a trenched gate;

implanting first conductive dopants into a surface of the semiconductor substrate adjacent to the trenched gate to form a first doping region;

depositing an insulating layer over the semiconductor substrate;

selectively etching the insulating layer to form a source contact window over a central portion of the first doping region and to leave an insulator structure above the trenched gate, the source contact window of the insulating layer having an enlarged, top portion which is larger in size than a bottom portion of the source contact window closer to the first doping region than the enlarged top portion; and

implanting second conductive dopants through the source contact window to form a second doping region in the central portion of the first doping region, at least a portion of the second doping region being formed by changing a conductive type of the central portion of the first doping region to a conductive type of the second conductive dopants.

2. The method of claim 1 further comprising performing a wet etching after implanting the second conductive dopants to reshape the insulator structure to form a rounded surface above the trenched gate.

3. The method of claim 1 wherein the first conductive dopants are N-type dopants, and the second conductive dopants are P-type dopants.

4. The method of claim 1 wherein the first conductive dopants are P-type dopants, and the second conductive dopants are N-type dopants.

5. The method of claim 1 wherein a junction depth of the first doping region is shallower than a junction depth of the second doping region.

6. The method of claim 1, wherein selectively etching the insulating layer comprises:

forming a photoresist pattern having an opening on the insulating layer above the first doping region; and

dry etching the insulating layer through the opening to form the source contact window having the enlarged top portion over the central portion of the first doping region and to leave the insulator structure above the trenched gate.

7. The method of claim 1 further comprising forming a conductive layer on the insulator structure, after implanting the second conductive dopants, to contact the source contact window.

8. The method of claim 7 wherein the conductive layer is made of aluminum or an aluminum alloy.

9. The method of claim 1 wherein the insulating layer comprises BPSG.

10. The method of claim 1 wherein the insulating layer comprises silicon oxide.

11. The method of claim 1 further comprising removing a portion of the first doping region and the second doping region from the surface of the semiconductor substrate, wherein the first doping region has a concentration of the first conductive dopants which is larger than a maximum concentration of the second conductive dopants in the second doping region.

12. The method of claim 1 wherein the first doping region is formed by implanting the first conductive dopants into the surface of the semiconductor substrate without using a mask.

13. A method of fabricating a DMOS transistor, the method comprising:

providing a semiconductor substrate having a gate oxide and a trenched gate;

implanting N-type dopants into a surface of the semiconductor substrate adjacent to the trenched gate to form an N-type doping region;

depositing an insulating layer over the semiconductor substrate;

forming a photoresist pattern having an opening above a central portion of the N-type doping region;

wet etching the insulating layer through the opening of the photoresist pattern to form an undercut structure in the insulating layer below the opening of the photoresist pattern;

dry etching the insulating layer through the opening of the photoresist pattern to form a source contact window over the central portion of the N-type doping region and to leave an insulator structure under the photoresist pattern and above the trenched gate, the source contact window of the insulating layer having an enlarged top portion formed by the undercut structure;

implanting P-type dopants through the source contact window to form a P-type doping region in the central portion of the N-type doping region, at least a portion of the P-type doping region being formed by reversing a conductive type of the central portion of the N-type doping region; and

removing the photoresist pattern.

14. The method of claim 13 further comprising performing a wet etching after removing the photoresist pattern to reshape the insulator structure to form a rounded surface above the trenched gate.

15. The method of claim 14 further comprising forming a conductive layer on the insulator structure to contact the source contact window.

16. The method of claim 13 wherein the conductive layer is made of aluminum or an aluminum alloy.

17. The method of claim 13 wherein the insulating layer comprises BPSG.

18. The method of claim 13 wherein the insulating layer comprises silicon oxide.

19. The method of claim 13 wherein a junction depth of the N-type doping region is shallower than a junction depth of the P-type doping region.

20. The method of claim 13 wherein wet etching of the insulating layer is performed by buffered oxide etchant (BOE) or hydrogen fluoride (HF).

21. The method of claim 13 wherein dry etching of the insulating layer is performed by reactive ion etching (RIE).

22. The method of claim 13 wherein the N-type doping region is formed by implanting the N-type dopants into the surface of the semiconductor substrate without using a mask.