One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region

• US 6,661,042 B2
• Filed: 03/11/2002
• Issued: 12/09/2003
• Est. Priority Date: 03/11/2002
• Status: Expired due to Fees

• Current Assignee: Mosys Incorporated (Peraso, Inc.)
• Original Assignee: Monolithic System Technology
• Inventors: Hsu, Fu-Chieh
• Primary Examiner(s): Wilson, Allan R.
• Application Number:
  US10/095,901
• Publication Number:
  US 20030168677A1
• Time in Patent Office: 638 Days
• Field of Search: 257/239, 257/296
• US Class Current: 257/239
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell is provided that includes a field-effect transistor fabricated using a process compatible with a standard CMOS process. The field-effect transistor includes a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region. A buried region of the first conductivity type is located under the source region, drain region and floating body region. The buried region helps to form a depletion region, which is located between the buried region and the source region, the drain region and the floating body region. The floating body region is thereby isolated by the depletion region. A bias voltage can be applied to the buried region, thereby controlling leakage currents in the 1T/FB DRAM cell.

Claims

1. A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell comprising:

a field-effect transistor having a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region;

a buried region of the first conductivity type located under the source region, drain region and floating body region; and

a depletion region located between the buried region and the source region, the drain region and the floating body region, wherein the depletion region provides the sole lateral isolation for portions of the floating body region.

2. The 1T/FB DRAM cell of claim 1, further comprising a bias voltage source coupled to the buried region.

3. The 1T/FB DRAM cell of claim 1, wherein the first conductivity type is N-type, and the second conductivity type is P-type.

4. The 1T/FB DRAM cell of claim 3, further comprising a bias voltage source coupled to the buried region, wherein the bias voltage source provides a nominal voltage between −

0.5 Volt and a V_CC supply voltage.

5. The 1T/FB DRAM cell of claim 1, wherein the first conductivity type is P-type, and the second conductivity type is N-type.

6. The 1T/FB DRAM cell of claim 5, further comprising a bias voltage source coupled to the buried region, wherein the bias voltage source provides a nominal voltage between 0 Volts and a V_CC supply voltage plus 0.5 Volts.

7. The 1T/FB DRAM cell of claim 1, wherein the buried region is grounded.

8. The 1T/FB DRAM cell of claim 1, wherein the buried region is floating.

9. The 1T/FB DRAM cell of claim 1, further comprising one or more shallow trench isolation (STI) regions, each having a bottom surface, the one or more STI regions being located adjacent to the source region and the drain region, wherein a top interface of the buried region is located at or above the bottom surface of the one or more STI regions and below the source region and the drain region.

10. The 1T/FB DRAM cell of claim 9, wherein a bottom interface of the buried region is located below the bottom surface of the one or more STI regions.

11. The 1T/FB DRAM cell of claim 1, wherein the buried region is formed by ion implantation.

12. A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell comprising:

a field-effect transistor having a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region;

a buried region of the first conductivity type located under the source region, drain region and floating body region;

a depletion region located between the buried region and the source region, the drain region and the floating body region; and

a deep well region of the first conductivity type located below and continuous with the buried region.

13. A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell comprising:

a field-effect transistor having a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region;

a buried region of the first conductivity type located under the source region, drain region and floating body region;

a depletion region located between the buried region and the source region, the drain region and the floating body region; and

a well region of the first conductivity type continuous with the buried region.

14. An array of one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cells comprising:

a first field-effect transistor having a first source region and a first drain region of a first conductivity type and a first floating body region of a second conductivity type, opposite the first conductivity type, located between the first source region and the first drain region;

a second field-effect transistor having a second source region and a second drain region of the first conductivity type, wherein the first drain region is continuous with the first drain region, and a second floating body region of the second conductivity type, located between the second source region and the second drain region;

a buried region of the first conductivity type located under the first and second source regions, the first and second drain regions and the first and second floating body regions; and

a depletion region located between the buried region and the first and second source regions, the first and second drain regions and the first and second floating body regions, wherein the depletion region provides the sole lateral isolation between the first and second floating body regions.

15. The array of claim 14, further comprising a single contact providing a connection to the first and second drain regions.