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One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region

  • US 6,661,042 B2
  • Filed: 03/11/2002
  • Issued: 12/09/2003
  • Est. Priority Date: 03/11/2002
  • Status: Expired due to Fees
First Claim
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1. A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell comprising:

  • a field-effect transistor having a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region;

    a buried region of the first conductivity type located under the source region, drain region and floating body region; and

    a depletion region located between the buried region and the source region, the drain region and the floating body region, wherein the depletion region provides the sole lateral isolation for portions of the floating body region.

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