Semiconductor device including inversely tapered gate electrode and manufacturing method thereof

• US 6,661,066 B2
• Filed: 09/22/1999
• Issued: 12/09/2003
• Est. Priority Date: 05/21/1999
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kuroi, Takashi, Itoh, Yasuyoshi, Horita, Katsuyuki, Shiozawa, Katsuomi
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Ha, Nathan W.
• Application Number:
  US09/401,849
• Publication Number:
  US 20020008293A1
• Time in Patent Office: 1,539 Days
• Field of Search: 257/412, 257/313, 257/314, 257/315, 257/336, 257/349, 257/365, 257/316, 257/413
• US Class Current: 257/412
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A semiconductor device and manufacturing method including a MOSFET having a trench-type element isolation structure (2) formed on a main surface of a semiconductor substrate (1). A pair of extensions (3) and source/drain regions (4) are selectively formed in the main surface so as to face each other through a channel region (50), a silicon oxide film (5) is formed on the trench-type element isolation structure (2) and on the source/drain regions (4) through a silicon oxide film (12), sidewalls (6) are formed on sides of the silicon oxide film (5), a gate insulating film (7) is formed on the main surface in a part where the channel region (50) is formed and a gate electrode (8) is formed to fill a recessed portion in an inversely tapered shape formed by the sides of the sidewalls (6) and the upper surface of the gate insulating film (7).

Claims

1. A semiconductor device, comprising:

a substrate;

source/drain regions formed in a main surface of said substrate with a channel region interposed therebetween;

a first insulating film formed on said main surface of said substrate in an area in which said source/drain regions are formed;

sidewalls composed of a second insulating film and formed on sides of said first insulating film;

a gate insulating film composed of a third insulating film and formed on said main surface of said substrate in an area in which said channel region is formed;

a gate electrode formed to fill an inversely tapered recessed portion formed by sides of said sidewalls and an upper surface of said gate insulating film; and

a fourth insulation film formed on an upper surface of said gate electrode and surrounding said gate electrode with said sidewalls,

wherein said gate electrode is inversely tapered such that a gate length continuously gradually diminishes from a top portion to a bottom portion until the bottom reaches the gate insulation film such that the gate length at the bottom portion of the gate electrode is narrower that the gate length at the top portion of the gate electrode,

wherein said third insulation film is composed of a material having a dielectric constant higher that that of said first insulating film, and is formed only on said main surface of said substrate and said sides of said sidewalls, and

wherein said second and fourth insulation films are composed of a material which is different from that of said first insulation film.

2. A semiconductor device, comprising:

a substrate;

source/drain regions formed in a main surface of said substrate with a channel region interposed therebetween;

a first insulating film formed on said main surface of said substrate in an area in which said source/drain regions are formed;

sidewalls composed of a second insulating film and formed on sides of said first insulating film;

a gate insulating film composed of a third insulating film and formed on said main surface of said substrate in an area in which said channel region is formed; and

a gate electrode formed to fill an inversely tapered recessed portion formed by sides of said sidewalls and an upper surface of said gate insulating film,

wherein said gate electrode is inversely tapered such that a gate length continuously gradually diminishes from a top portion to a bottom portion until the bottom portion reaches the gate insulating film such that the gate length at the bottom portion of the gate electrode is narrower than the gate length at the top portion of the gate electrode,

wherein said third insulating film is composed of a material having a dielectric constant higher that that of said first insulating film, and is formed only on said main surface of said substrate and said sides of said sidewalls, and

wherein said gate electrode has its peripheral part formed to extend on an upper surface of said first insulating film.