Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack

• US 6,661,085 B2
• Filed: 02/06/2002
• Issued: 12/09/2003
• Est. Priority Date: 02/06/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kim, Sarah E., List, R. Scott, Kellar, Scot A.
• Primary Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US10/066,668
• Publication Number:
  US 20030148590A1
• Time in Patent Office: 671 Days
• Field of Search: 438/12, 438/51, 438/455, 438/458, 438/459, 438/975, 438/977, 438/107, 438/109, 257/686, 257/687, 257/723, 257/724, 257/717
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/09517 including bonding areas providing primarily mechanical support
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/13166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/81121 : Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/8182 : Diffusion bonding
• CPC Class Codes: H01L 2224/81894 : Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/585 : comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface; and a second wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface, wherein the metallic lines and the barrier line deposited on the surface of the second wafer are bonded with the metallic lines and the barrier line deposited on the surface of the first wafer to establish electrical connections between active IC devices on adjacent wafers and to form a barrier structure on the outer edge of the adjacent wafers.

Claims

1. A three-dimensional (3-D) integrated chip system, comprising:

a first wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface; and

a second wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface, wherein the metallic lines and the barrier line deposited on the surface of the second wafer are bonded with the metallic lines and the barrier line deposited on the surface of the first wafer to establish electrical connections between active IC devices on adjacent wafers and to form a barrier structure on the outer edge of the adjacent wafers.

2. The three-dimensional (3-D) integrated chip system as claimed in claim 1, wherein the metallic lines include Copper (Cu) bonding pads deposited on opposing surfaces of the adjacent wafers to serve as electrical contacts between active IC devices on both the adjacent wafers.

3. The three-dimensional (3-D) integrated chip system as claimed in claim 1, wherein the bonded wafers includes a plurality of individual die and the barrier structure is formed to protect internal die from corrosion, contamination and crack propagation when the bonded wafers are cut into individual die.

4. The three-dimensional (3-D) integrated chip system as claimed in claim 3, wherein the barrier structure is a dense grid of connected copper (Cu) lines in a checkerboard pattern erected on the outer edge of usable die.

5. The three-dimensional (3-D) integrated chip system as claimed in claim 4, wherein the barrier structure is erected on the outer edge of usable die using an edge reticle.

6. The three-dimensional (3-D) integrated chip system as claimed in claim 1, wherein the bonded wafers correspond to a single die and the barrier structure is formed by one or more barrier lines deposited on the outer edge of the bonded die to protect the bonded die from corrosion, contamination and crack propagation.

7. The three-dimensional (3-D) integrated chip system as claimed in claim 6, wherein the barrier lines correspond to concentric copper (Cu) guard rings deposited on the perimeter of the bonded die to serve as passivation barriers.

8. A three-dimensional (3-D) integrated chip system, comprising:

a first wafer including one or more active integrated circuit (IC) devices;

a second wafer including one or more active integrated circuit (IC) devices;

first metallic lines deposited on opposing surfaces of the first and second wafers at designated locations to serve as wafer bonding pads and to establish electrical connections between active IC devices on the first and second wafers, when the first and second wafers are bonded; and

second metallic lines deposited on an outer edge of opposing surfaces of the first and second wafers to form a barrier structure, when the first and second wafers are bonded.

9. The three-dimensional (3-D) integrated chip system as claimed in claim 8, wherein the first metallic lines include a plurality of Copper (Cu) bonding pads deposited on opposing surfaces of the adjacent wafers to serve as electrical contacts between active IC devices on both the adjacent wafers.

10. The three-dimensional (3-D) integrated chip system as claimed in claim 8, wherein the second metallic lines include a plurality of Copper (Cu) barrier lines deposited on the outer edge of the adjacent wafers to protect active IC devices from corrosion and contamination.

11. The three-dimensional (3-D) integrated chip system as claimed in claim 8, wherein the barrier structure is a dense grid of connected copper (Cu) lines in a checkerboard pattern erected on the outer edge of usable die within bonded wafers.

12. The three-dimensional (3-D) integrated chip system as claimed in claim 11, wherein the barrier structure is erected on the outer edge of usable die using an edge reticle.

13. The three-dimensional (3-D) integrated chip system as claimed in claim 8, wherein the bonded wafers correspond to a single die and the barrier structure is formed to protect the bonded die from corrosion, contamination and crack propagation.

14. The three-dimensional (3-D) integrated chip system as claimed in claim 13, wherein the second metallic lines correspond to concentric copper (Cu) guard rings deposited on the perimeter of the bonded die to serve as passivation barriers.