Memory module

• US 6,661,092 B2
• Filed: 07/25/2002
• Issued: 12/09/2003
• Est. Priority Date: 07/26/2001
• Status: Expired due to Term

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Nishio, Yoji, Shibata, Kayoko
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nguyen, Dao H.
• Application Number:
  US10/205,040
• Publication Number:
  US 20030037216A1
• Time in Patent Office: 502 Days
• Field of Search: 257/685, 257/686, 257/724, 257/777
• US Class Current: 257/724
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A memory module is provided with a resistor serving as an impedance adjuster which is connected directly or indirectly to an output terminal of an output transistor of a C/A register. The resistor adjusts the output impedance of the C/A register viewed from an input terminal of a C/A bus in such a manner that the output impedance becomes substantially constant within an operating voltage range of an internal signal output from the C/A register. The memory module is further provided with a capacitor serving as a rise time/fall time adjuster which adjusts rise time and fall time of the internal signal to specific values such that satisfactory waveforms are obtained.

Claims

1. A memory module comprising:

a command/address register device for generating an internal signal according to an external command/address signal, said command/address register device having an output transistor;

a plurality of memory devices divided into first and second groups;

wiring interconnecting said command/address register device and said memory devices; and

a substrate on which said command/address register device and said multiple memory devices are mounted;

wherein said wiring includes;

a first wiring section extending from said command/address register device to a first branch point;

a second wiring section extending from the first branch point to a second branch point;

a third wiring section extending from the first branch point to a third branch point;

a fourth wiring section which branches out from the second branch point and extends up to the memory devices of said first group; and

a fifth wiring section which branches out from the third branch point and extends up to the memory devices of said second group; and

said command/address register device includes;

an impedance adjuster for adjusting the output impedance of said command/address register device viewed from a junction point between said command/address register device and the first wiring section in such a manner that said output impedance becomes substantially constant within an operating voltage range of the internal signal; and

a rise time/fall time adjuster for adjusting rise time and fall time of the internal signal to specific values.

2. The memory module according to claim 1, wherein neither of said multiple memory devices nor said wiring is terminated.

3. The memory module according to claim 1, wherein said command/address register device is a command/address register including said output transistor and having a register output terminal, said command/address register device including a resistor connected to the register output terminal in series, the resistor serving as the impedance adjuster.

4. The memory module according to claim 3, wherein the resistance of the resistor is larger than the on-state resistance of the output transistor.

5. The memory module according to claim 1, wherein said command/address register device is a command/address register incorporating a resistor serving as the impedance adjuster.

6. The memory module according to claim 1, wherein the impedance adjuster includes first and second resistors, and said command/address register device is a command/address register having a register output terminal and includes the second resistor connected to the register output terminal, the command/address register including the output transistor and the first resistor which is connected between an output terminal of the output transistor and the register output terminal in series.

7. The memory module according to claim 6, wherein the resistance of the first resistor is set to a value which is smallest in consideration of potentially selected numbers of said memory devices, and the resistance of the second resistor is set to a value to be added to the resistance of the first resistor for properly adjusting said output impedance.

8. The memory module according to claim 6, wherein the combined resistance of the first and second resistors is larger than the on-state resistance of the output transistor.

9. The memory module according to claim 1, wherein the command/address it register incorporates a capacitor serving as the rise time/fall time adjuster.

10. The memory module according to claim 1, wherein the impedance adjuster adjusts said output impedance according to the number of said memory devices mounted on said substrate.

11. The memory module according to claim 6, wherein said specific values of the rise time and the fall time remain constant regardless of the potentially selected numbers of said memory devices.

12. The memory module according to claim 11, wherein the frequency of the internal signal is at least 100 MHz.

13. The memory module according to claim 12, wherein the rise time and the fall time fall within a range of 0.9 ns to 2.0 ns.

14. The memory module according to claim 1, wherein the number of the memory devices of said first group is larger than the number of the memory devices of said second group by a specific number and all the memory devices have substantially the same input capacitance with one another, said memory module further comprising:

said specific number of dummy capacitors connected to the fifth wiring section together with the memory devices of said second group, each of the dummy capacitors having substantially the same input capacitance as the individual memory devices;

wherein the combined impedance of the memory devices of said first group viewed from the second branch point is equal to the combined impedance of the memory devices of said second group and the dummy capacitors viewed from the third branch point.

15. The memory module according to claim 14, wherein the second and third wiring sections have equal line impedance and the fourth and fifth wiring sections have equal line impedance.

16. The memory module according to claim 14, wherein the fourth wiring section forms a local topology in which nodes of the memory devices of said first group are arranged symmetrically with respect to a first imaginary line passing through the second branch point, and the fifth wiring section forms a local topology in which nodes of the memory devices of said second group and said specific number of the dummy capacitors are arranged symmetrically with respect to a second imaginary line passing through the third branch point.

17. The memory module according to claim 1, wherein the number of the memory devices of said first group is larger than the number of the memory devices of said second group by a specific number and all the memory devices have substantially the same input capacitance with one another, and line lengths of the second to fifth wiring sections are determined in such a manner that the combined impedance of the memory devices of said first group viewed from the first branch point is equal to the combined impedance of the memory devices of said second group viewed from the first branch point.

18. The memory module according to claim 1, wherein the number of the memory devices of said first group is 8 or 10 while the number of the memory devices of said second group is 8, and the line impedance of the first to fifth wiring sections substantially falls within a range of 50 to 65 ohms while said output impedance is 20 ohms ±

20%.

19. The memory module according to claim 1, wherein the number of the memory devices of said first group is 4 or 5 while the number of the memory devices of said second group is 4, and the line impedance of the first to fifth wiring sections substantially falls within a range of 50 to 65 ohms while said output impedance is 25 ohms ±

20%.

20. The memory module according to claim 1, wherein the number of the memory devices of said first group is 2 or 3 while the number of the memory devices of said second group is 2, and the line impedance of the first to fifth wiring sections substantially falls within a range of 50 to 65 ohms while said output impedance is 30 ohms ±

20%.

21. The memory module according to claim 1 comprising a buffer device including said impedance adjuster and said rise time/fall time adjuster instead of said command/address register device.