Semiconductor device

• US 6,661,095 B2
• Filed: 08/19/2002
• Issued: 12/09/2003
• Est. Priority Date: 02/20/2002
• Status: Expired due to Fees

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ukita, Motomu
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US10/222,791
• Publication Number:
  US 20030157811A1
• Time in Patent Office: 477 Days
• Field of Search: 257/358, 257/359, 257/363, 257/379, 257/508, 257/748, 257/750, 257/758, 257/E29.204, 257/904, 257/774, 257/775
• US Class Current: 257/758
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 27/0802 Resistors only
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The structure around a high-resistance element is formed in mirror symmetry to a plane perpendicular to a semiconductor substrate and the surface of the sheet. Specifically, high-resistance element, contact plugs and extending portion of interconnection layers are symmetric, each of the interconnection layers covering high-resistance element by the same amount. Thus, a semiconductor device of which degree of freedom on designing layout of interconnections which is to be connected to interconnection layers electrically connected to the high-resistance element via contact plugs can be attained.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a resistance element formed above or within said semiconductor substrate;

an interlayer insulation film formed on said resistance element

a first contact hole penetrating said interlayer insulation film vertically and connected to said resistance element;

a second contact hole penetrating said interlayer insulation film vertically and connected to said resistance element;

a first interconnection layer formed on said interlayer insulation film and connected to said first contact hole; and

a second interconnection layer formed on said interlayer insulation film and connected to said second contact hole;

wherein

above a region between said first contact hole and said second contact hole, said first interconnection layer and said second interconnection layer are formed not in symmetry to a prescribed plane perpendicular to said semiconductor substrate, but formed as layers of the same thickness at the same height and in point symmetry on a plane parallel to said semiconductor substrate.

2. The semiconductor device according to claim 1, wherein

said resistance element is an impurity diffusion layer formed within said semiconductor substrate.

3. The semiconductor device according to claim 1, wherein

said resistance element is an interconnection layer formed on said semiconductor substrate.

4. The semiconductor device according to claim 1, wherein

an interval between said first interconnection layer and said second interconnection layer is set large enough for preventing electrical short therebetween, and is set large enough for suppressing an electric effect from an upper interconnection layer to said resistance element when said upper interconnection layer is provided in a region above said resistance element and further above said first interconnection layer and said second interconnection layer.

5. A semiconductor device, comprising:

a semiconductor substrate;

a resistance element formed above said semiconductor substrate;

an interlayer insulation film formed under said resistance element

a first contact hole penetrating said interlayer insulation film vertically and connected to said resistance element;

a second contact hole penetrating said interlayer insulation film vertically and connected to said resistance element;

a first conductive unit formed under said interlayer insulation film and connected to said first contact hole; and

a second conductive unit formed under said interlayer insulation film and connected to said second contact hole;

wherein

under a region between said first contact hole and said second contact hole, said first conductive unit and said second conductive unit are formed in symmetry to a prescribed plane perpendicular to said semiconductor substrate, or formed as layers of the same thickness at the same height and in point symmetry on a prescribed plane parallel to said semiconductor substrate.

6. The semiconductor device according to claim 5, wherein

an interval between said first conductive unit and said second conductive unit is set large enough for preventing electrical short therebetween, and is set large enough for suppressing an electric effect from a lower interconnection layer to said resistance element when said lower interconnection layer is provided in a region below said resistance element and further below said first conductive unit and said second conductive unit.

10. The semiconductor device according to claim 5, wherein

said resistance element is an interconnection layer.

7. A semiconductor device, comprising:

a semiconductor substrate;

a resistance element formed above said semiconductor substrate;

a first interlayer insulation film formed under said resistance element;

a second interlayer insulation film formed on said resistance element;

a first conductive unit formed under said first interlayer insulation film;

a second conductive unit formed under said first interlayer insulation film and not being identical to said first conductive unit;

a third conductive unit formed on said second interlayer insulation film;

a fourth conductive unit formed on said second interlayer insulation film and not being identical to said third conductive unit;

a first contact hole penetrating said first interlayer insulation film and second interlayer insulation film vertically and connected to said first conductive unit and said third conductive unit;

a second contact hole penetrating said first interlayer insulation film and second interlayer insulation film vertically and connected to said second conductive unit and said fourth conductive unit;

a third contact hole penetrating said second interlayer insulation film vertically and connected to said resistance element and said third conductive unit; and

a fourth contact hole penetrating said second interlayer insulation film vertically and connected to said resistance element and said fourth conductive unit;

wherein

under a region between said first contact hole and said second contact hole, said first conductive unit and said second conductive unit are formed in symmetry to a prescribed plane perpendicular to said semiconductor substrate, or formed as layers at the same height and in point symmetry on a prescribed plane parallel to said semiconductor substrate, and above the region between the third and the fourth contact holes, the third and the fourth conductive units are formed symmetrical to the prescribed plane perpendicular to the semiconductor substrate, or formed into layers of identical thickness and at the same height and in point symmetry on a prescribed plane parallel to the semiconductor substrate.

8. The semiconductor device according to claim 7, wherein

said first conductive unit and second conductive unit are impurity diffusion layers formed within said semiconductor substrate.

9. The semiconductor device according to claim 7, wherein

said first conductive unit and second conductive unit are interconnection layers formed above said semiconductor substrate.

11. The semiconductor device according to claim 7, wherein

an interval between said first conductive unit and said second conductive unit is set large enough for preventing electrical short therebetween, and is set large enough for suppressing an electric effect from a lower interconnection layer to said resistance element when said lower interconnection layer is provided in a region below said resistance element and further below said first conductive unit and said second conductive unit.

12. The semiconductor device according to claim 11, wherein

said lower conductive unit is a well formed within said semiconductor substrate.

13. The semiconductor device according to claim 11, wherein

said lower conductive unit is an interconnection layer formed on said semiconductor substrate.

14. A semiconductor device, comprising:

a semiconductor substrate;

a resistance element formed within said semiconductor substrate;

an interlayer insulation film formed on said resistance element

a first contact hole penetrating said interlayer insulation film vertically and connected to said resistance element;

a second contact hole penetrating said interlayer insulation film vertically and connected to said resistance element;

a first interconnection layer formed on said interlayer insulation film and connected to said first contact hole; and

a second interconnection layer formed on said interlayer insulation film and connected to said second contact hole;

wherein

above a region between said first contact hole and said second contact hole, said first interconnection layer and said second interconnection layer are formed in symmetry to a prescribed plane perpendicular to said semiconductor substrate, and

said resistance element is an impurity diffusion layer formed within said semiconductor substrate.

15. The semiconductor device according to claim 14, wherein

said resistance element is an interconnection layer formed on said semiconductor substrate.

16. The semiconductor device according to claim 14, wherein

an interval between said first interconnection layer and said second interconnection layer is set large enough for preventing electrical short therebetween, and is set large enough for suppressing an electric effect from an upper interconnection layer to said resistance element when said upper interconnection layer is provided in a region above said resistance element and further above said first interconnection layer and said second interconnection layer.