Low impedance power distribution structure for a semiconductor chip package
First Claim
1. A wire structure made from an under bump metallurgy (UTBM) process, said wire structure comprising:
- a substrate having a plurality of first features, wherein, said first features are under bump metallurgy;
a plurality of second features situated over at least one of said first features, said second features operatively connected to said first features;
at least one electrical wire interconnecting said plurality of first features, wherein said electrical wire is under bump metallurgy, said electrical wire comprising a metal structure having a low impedance and characterized by having substatiantially the same composition as the first features; and
wherein said first features and said electrical wire are formed in substantially the same plane.
8 Assignments
0 Petitions
Accused Products
Abstract
A low impedance power distribution structure and method for substrate packaging of semiconductor chips containing very large scale integrated circuit (VLSI) circuits, such as microprocessors and associated memory, is presented. The power distribution structure incorporates under bump metallurgy (UBM) solder bump forming technology to produce not only solder bump connections that are vertically oriented, but also low impedance distribution wires that are horizontally oriented, and which provide electrical interconnection between various selected electrical contact points, such as solder bumps. These low impedance distribution wires introduce the benefits of low characteristic impedance to the substrate'"'"'s power distribution structure.
-
Citations
20 Claims
-
1. A wire structure made from an under bump metallurgy (UTBM) process, said wire structure comprising:
-
a substrate having a plurality of first features, wherein, said first features are under bump metallurgy;
a plurality of second features situated over at least one of said first features, said second features operatively connected to said first features;
at least one electrical wire interconnecting said plurality of first features, wherein said electrical wire is under bump metallurgy, said electrical wire comprising a metal structure having a low impedance and characterized by having substatiantially the same composition as the first features; and
wherein said first features and said electrical wire are formed in substantially the same plane. - View Dependent Claims (2, 3, 4, 5)
-
-
6. An electronic package comprising:
-
a first substrate having a first surface, said first surface including a plurality of first features;
a second substrate having a second surface, said second surface including a plurality of second features, wherein said second substrate is positioned substantially parallel to said first substrate, and wherein said second surface is located proximal to and facing said first surface;
first electrical wires located on said first surface, said first electrical wires connecting selected ones of said plurality of first features on said first surface, wherein said first features and said first electrical wires are formed in substantially the same first plane;
second electrical wires located on said second surface, said second electrical wires connecting selected ones of said second plurality of second features on said second surface, wherein said second features and said second electrical wires are formed in substantially the same second plane;
wherein said first substrate and said second substrate are operationally bonded together; and
wherein said first electrical wires, said second electrical wires, and said first features are under bump metallurgy (UBM). - View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
-
-
14. A method of forming an electronic package comprising:
-
providing a first substrate having a first surface, said first surface including a plurality of first features;
providing a second substrate having a second surface, said second surface including a plurality of second features, wherein said second substrate is positioned substantially parallel to said first substrate, and wherein said second surface is located proximal to and facing said first surface;
providing first electrical wires located on said first surface, said first electrical wires connecting selected ones of said plurality of first features on said first surface, wherein said first features and said first electrical wires are formed in substantially the same first plane;
providing second electrical wires located on said second surface, said second electrical wires connecting selected ones of said plurality of second features on said second surface, wherein said second features and said second electrical wires are formed in substantially the same second plane;
wherein said first substrate and said second substrate are operationally bonded together; and
forming said first electrical wires, said second electrical wires, said first features, and said second features with under bump metallurgy (UBM) processing. - View Dependent Claims (15, 16, 17, 18, 19, 20)
-
Specification