MOSFET driver matching circuit for an enhancement mode JFET

• US 6,661,276 B1
• Filed: 07/29/2002
• Issued: 12/09/2003
• Est. Priority Date: 07/29/2002
• Status: Active Grant

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Lovoltech Incorporated
• Inventors: Chang, Daniel
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US10/209,211
• Time in Patent Office: 498 Days
• Field of Search: 327/430, 327/427, 327/431, 327/434, 327/437, 327/108, 327/110, 333/81.R
• US Class Current: 327/427
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 17/6877 the control circuit comprising active elements different from those used in the output circuit

Abstract

A matching circuit for coupling a conventional metal-oxide semiconductor field effect transistor (MOSFET) driver to the gate of a junction field effect transistor (JFET). A driver circuit optimized for driving a MOSFET is combined with a matching circuit to provide gate drive for a JFET. The matching circuit comprises a resistor and capacitor in parallel. For driving enhancement mode JFETs having a gate grid array structure and a pinch-off voltage greater than 0.4 volts, the range of resistor values is 10 to 200 ohms, and the range of capacitor values is 1 to 100 nF. For devices having a pinch-off voltage less than 0.4 volts, the range of resistor values is 100 to 2000 ohms. The matching circuit may further include a diode to provide a bias.

Claims

1. A switching circuit comprising;

a metal-oxide semiconductor field effect transistor (MOSFET) driver having a signal input, a supply voltage input, and an output;

an enhancement mode junction field effect transistor (JFET) having a gate, a source and a drain; and

a matching circuit comprising a capacitor and a resistor coupled in parallel, wherein said matching circuit is coupled to said output and also coupled to said gate.

2. The switching circuit of claim 1, wherein said gate comprises a gate grid array.

3. The switching circuit of claim 1, further comprising a supply voltage coupled to said supply voltage input, wherein said supply voltage is less than 5 volts.

4. The switching circuit of claim 1, further comprising a supply voltage coupled to said supply voltage input, wherein said supply voltage is less than 5 volts.

5. The switching circuit of claim 1, further comprising a signal received at said signal input, wherein said signal has a frequency substantially between 100 kHz and 6 MHz.

6. The switching circuit of claim 1, further comprising a signal received at said signal input, wherein said signal has an amplitude substantially of 5 volts or less.

7. The switching circuit of claim 1, further comprising a signal received at said signal input, wherein said signal has a frequency substantially between 100 kHz and 6 MHz.

8. The switching circuit of claim 1, wherein said capacitor has a capacitance substantially between 1 nF and 100 nF.

9. The switching circuit of claim 1, wherein said resistor has a resistance substantially between 10 ohms and 200 ohms.

10. A matching circuit for coupling a driver circuit optimized for a MOSFET to the gate of an enhancement mode JFET, said matching circuit comprising a capacitor coupled in parallel with a resistor.

11. The matching circuit of claim 10, wherein said capacitor has a capacitance substantially between 1 nF and 100 nF.

12. The matching circuit of claim 10, wherein said resistor has a resistance substantially between 10 ohms and 200 ohms.

13. The matching circuit of claim 10, wherein said enhancement mode JFET comprises a gate grid array.

14. The matching circuit of claim 10, further including at least one diode coupled in series with said resistor.

15. The matching circuit of claim 14, wherein a plurality of diodes are coupled in series with said resistor.

16. A power conditioning circuit comprising:

a driver circuit optimized for a MOSFET having a signal input and an output;

an enhancement mode junction field effect transistor (JFET) having a gate, a source and a drain; and

a matching circuit comprising a capacitor and a resistor coupled in parallel, wherein said matching circuit is coupled to said output and also coupled to said gate.

17. The power conditioning circuit of claim 16, wherein said gate comprises a gate grid array.

18. The power conditioning circuit of claim 16, further comprising a signal received at said signal input, wherein said signal has a frequency substantially between 100 kHz and 6 MHz.

19. The power conditioning circuit of claim 16, further comprising a signal received at said signal input, wherein said signal has an amplitude substantially of 5 volts or less.

20. The power conditioning circuit of claim 16, further comprising a signal received at said signal input, wherein said signal has a frequency substantially between 100 kHz and 6 MHz.

21. The power conditioning circuit of claim 16, wherein said capacitor has a capacitance substantially between 1 nF and 100 nF.

22. The power conditioning circuit of claim 16, wherein said resistor has a resistance substantially between 10 ohms and 200 ohms.