Emissive display using organic electroluminescent devices

• US 6,661,397 B2
• Filed: 08/29/2001
• Issued: 12/09/2003
• Est. Priority Date: 03/30/2001
• Status: Expired due to Term

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Hitachi, Ltd.
• Inventors: Mikami, Yoshiro, Ouchi, Takayuki, Kaneko, Yoshiyuki, Sato, Toshihiro
• Primary Examiner(s): Shalwala, Bipin
• Assistant Examiner(s): Kovalick, Vincent E.
• Application Number:
  US09/940,886
• Publication Number:
  US 20020140641A1
• Time in Patent Office: 832 Days
• Field of Search: 345/36, 345/42, 345/45, 345/55, 345/76, 345/77, 345/82, 345/83, 345/90, 345/98, 345/204, 345/205, 345/214, 345/690, 315/169.3, 340/825.81
• US Class Current: 345/76
• CPC Class Codes: G09G 2300/0439 Pixel structures
• CPC Class Codes: G09G 2300/0465 Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements

Abstract

An emissive display using an organic electroluminescent device is provided, in which the pixel circuit is simplified, the aperture ratio is increased, high resolution is achieved, and the power consumption is reduced. In the configuration, among the two sets of inverter circuits, one set of inverter circuit is formed by a circuit connecting an organic electoluminescent device and a transistor in series, and a transistor of a memory circuit is omitted. Also, in the mutual connection of the two sets of inverters, display data is inputted to a line connected to the gate of the transistor connected in series with the organic electoluminescent device, and owing to this connection, the write load is reduced, and the high resolution is achieved by enabling to write at high speed.

Claims

1. An emissive display having pixels enclosed by a plurality of scan lines, and a plurality of signal lines intersecting with each other, wherein

each pixel includes a memory circuit including first and second inverter circuits, said first inverter circuit including an electroluminescent device formed by an organic multi-layers driven by a current as a load device, and including a display control circuit connecting in series a main circuit of at least one first transistor, and

said memory circuit stores display information of said pixel according to a conduction state or a non-conduction state of the main circuit of the first inverter, and controls an on state and an off state of said electroluminescent device on a binary basis.

2. An emissive display according to claim 1, wherein

said second inverter circuit uses a CMOS transistor.

3. An emissive display according to claim 1, wherein

said memory circuit constitutes a bistable circuit in which an input terminal of one of said first and second inverter circuits is mutually connected to an output terminal of the other of said first and second inverter circuits, and

a gate terminal portion of the transistor forming said first inverter circuit is connected to said signal line through a main circuit of a second transistor, and a gate of said second transistor is connected to the scan line, thereby to provide an input circuit for inputting data to be stored in said memory circuit.

10. An emissive display according to claim 1, wherein

in said pixel, a relationship of an aperture ratio <

an average brightness/3000 is present between the aperture ratio and the average brightness, where the aperture ratio is the area ratio of the area of light emission area to the pixel area.

11. An emissive display according to claim 1, wherein

a power supply and reference voltage line of said inverter circuit are arranged in a vertical direction of the pixel, and a relationship of an aperture ratio <

an average brightness/3000 is present between the aperture ratio and the average brightness, where the aperture ratio is the area ratio of the area of light emission area to the pixel area.

4. An emissive display having a pixel enclosed by a plurality of scan lines, and a plurality of signal lines intersecting with each other, wherein

said pixel includes a memory circuit including first and second inverter circuits, said first inverter circuit including an electroluminescent device formed by an organic multi-layers driven by a current as a load device, and including a display control circuit connecting in series a main circuit of at least one first transistor,

said memory circuit constitutes a bistable circuit in which an input terminal of one of said first and second inverter circuits is connected to an output terminal of the other of said first and second inverter circuits, and

in said memory circuit display information of said pixel is stored in response to a conduction state and a non-conduction state of the main circuit of the first inverter, and an on state and an off state of said electrpluminescent device are binary controlled, and

a series-parallel conversion circuit using a shift register is provided at around the display region aligned with said pixel, and an output of each stage of said shift register is connected to the signal line.

5. An emissive display having a pixel enclosed by a plurality of scan lines, and a plurality of signal lines intersecting with each other, said emissive display comprising a memory circuit including:

a first inverter circuit including a main circuit of a third transistor and an organic electroluminescent device connected in series between a power supply line and a reference voltage line;

a sampling circuit connected to an input terminal of said first inverter circuit for controlling the connection with said signal line in response to a scan pulse applied through said scan line;

a set circuit for controlling the connection between said power supply line and the input terminal of said first inverter circuit, by an output of said first inverter circuit; and

a reset circuit for controlling the connection between the reference voltage line and the input terminal of said first inverter circuit, by a signal voltage sampled by said sampling circuit, wherein

in said memory circuit, display information of the pixel is stored in response to a conduction state and a non-conduction state of the main circuit of the first inverter, and an on state and an off state of said electroluminescent device are binary controlled.

6. An emissive display according to claim 5, wherein

in said set circuit or said reset circuit, there is provided with an AC coupling circuit formed by using a capacitance and a diode or a resistor in order to apply an input signal exceeding a voltage of the power supply or the reference voltage to a gate terminal of the transistor, and

all the transistors of said pixel are formed by P-type or N-type.

7. An emissive display according to claim 5, wherein

a signal shift register capable of outputting a binary signal is connected to said signal line, and a scan line driver circuit generating a scan pulse to select the pixel is connected to said scan line, and

an initialized period is provided in said signal shift register so that said signal line applies a logical signal to turn off said electoluminescent device within a scan pulse period.

8. An emissive display having pixels enclosed by a plurality of scan lines, and a plurality of signal lines intersecting with each other, wherein

each pixel includes a memory circuit including first and second inverter circuits,

said first and second inverter circuits include an electroluminescent device formed by a multi-layers driven by a current as a load device, and a display control circuit connecting in series a main circuit of at least one first transistor,

said memory circuit stores display information of said pixel according to a conduction state or a non-conduction state of the main circuit of the inverter, and includes covering means to cover the electroluminescent device of said second inverter circuit, and controls an on state and an off state of said electroluminescent device on a binary basis.

9. An emissive display having a pixel enclosed by a plurality of scan lines, and a plurality of signal lines intersecting with each other, wherein

said pixel includes a memory circuit including an inverter circuit, said inverter circuit includes an electroluminescent device formed by organic multi-layers driven by a current as a load device, and a display control circuit connecting in series a main circuit of at least one first transistor,

said memory circuit stores, display information of the pixel according to a conduction state or a non-conduction state of the main circuit of the inverter, and controls an on state and an off state of said electroluminescent device on a binary basis.