Video and graphics system with MPEG specific data transfer commands

• US 6,661,422 B1
• Filed: 08/18/2000
• Issued: 12/09/2003
• Est. Priority Date: 11/09/1998
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Valmiki, Ramanujan K., Kumar, Sathish
• Primary Examiner(s): Bella, Matthew C.
• Assistant Examiner(s): Sajous, Wesner
• Application Number:
  US09/643,223
• Time in Patent Office: 1,208 Days
• Field of Search: 345/629, 345/634-639, 345/768, 345/790, 345/796, 345/799, 345/784, 345/788, 345/759, 345/806, 345/809, 345/839, 345/501-503, 345/506, 345/519, 345/530-532, 345/534-538, 345/541, 345/543, 345/547-549, 345/555-556, 345/557, 345/574, 348/460, 348/461, 348/467, 348/474, 348/571, 348/723, 348/725, 386/27, 386/33-37, 386/40, 386/64-68, 386/46, 386/101, 386/109, 725/63-72, 725/105, 725/88-90, 725/148, 370/468-471, 370/473-480
• US Class Current: 345/530
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/28 for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 : for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 : characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 : using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 : Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 21/42204 : User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor constructive details of casings for the remote control device H01H9/0235; user interfaces for controlling a tuning device of a television receiver through a remote control H03J9/00; remote control of peripheral devices connected to a television receiver through the remote control device of the television receiver H04B1/205
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/4438 : Window management, e.g. event handling following interaction with the user interface
• CPC Class Codes: H04N 21/47 : End-user applications
• CPC Class Codes: H04N 5/126 : whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/0135 : involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 : Multi-standard receivers

Abstract

A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data containing SDTV video data or HDTV video data. The video decoding system includes a video decoder for processing the compressed video data to generate displayable video, and a memory controller for transferring the compressed video data to and from an external memory. The video decoder requests to the memory controller to transfer the compressed video data using one of predetermined addressing patterns. The predetermined addressing patterns allow for more efficient transferring of the compressed video data to and from the external memory when compared to sequentially transferring a fixed number of data bytes starting at a fixed address. The use of the predetermined addressing patterns results in reading the compressed video data from the external memory in a predetermined order in a less number of clock cycles. The use of the predetermined addressing patterns also results in transferring the compressed video data over the data bus between the memory controller and the video decoder in a less number of clock cycles.

Claims

1. A method of accessing a memory for processing compressed video data comprising the steps of:

requesting to transfer the compressed video data using one of a plurality of addressing patterns, one or more of the addressing patterns being predetermined;

reading the compressed video data from the memory using a first one of the addressing patterns if a read operation has been requested; and

writing the compressed video data to the memory using a second one of the addressing patterns if a write operation has been requested,

wherein the predetermined addressing patterns allow for transferring of the requested compressed video data in less clock cycles as compared to sequentially transferring a fixed number of data bytes starting at a fixed address.

2. The method of accessing a memory of claim 1 wherein the compressed video data includes macroblocks representing MPEG-2 video data, and the predetermined addressing patterns allow for more efficient transferring of the macroblocks when compared to sequentially transferring a fixed number of data bytes starting at a fixed address.

3. The method of accessing a memory of claim 2 wherein the macroblocks are transferred in a predetermined order when the predetermined addressing patterns are used to transfer the macroblocks.

4. The method of accessing a memory of claim 2 wherein the MPEG-2 video data is organized in the memory in a manner suitable for MPEG-2 video decoding.

5. The method of accessing a memory of claim 2 wherein the predetermined addressing patterns allow for reading of the macroblocks needed for decoding the compressed video data from the memory in less clock cycles when compared to sequentially transferring the fixed number of data bytes starting at the fixed address.

6. The method of accessing a memory of claim 2 wherein the predetermined addressing patterns allow for transferring of the macroblocks needed for decoding the compressed video data over a data bus in less clock cycles when compared to sequentially transferring the fixed number of data bytes starting at the fixed address.

7. The method of accessing a memory of claim 1 wherein the addressing patterns include programmable addressing patterns that can change based on data transfer requirements.

8. The method of accessing a memory of claim 1 wherein the compressed video data include at least one of HDTV video data and SDTV video data.

9. A video decoding system comprising:

a video decoder for processing compressed video data to generate displayable video; and

a memory controller for transferring the compressed video data to and from a memory,

wherein the video decoder requests to the memory controller to transfer the compressed video data using one of a plurality of addressing patterns that allow for transferring of the requested compressed video data in less clock cycles as compared to sequentially transferring a fixed number of data bytes starting at a fixed address.

10. The video decoding system of claim 9 wherein the video decoder and the memory controller are integrated on an integrated circuit chip.

11. The video decoding system of claim 9 wherein the compressed video data includes macroblocks representing MPEG-2 video data, the addressing patterns include predetermined addressing patterns, and the predetermined addressing patterns allow for more efficient transferring of the macroblocks when compared to sequentially transferring a fixed number of data bytes starting at a fixed address.

12. The video decoding system of claim 11 wherein the macroblocks are transferred in a predetermined order when the predetermined addressing patterns are used to transfer the macroblocks.

13. The video decoding system of claim 11 wherein the MPEG-2 video data is organized in the memory in a manner suitable for MPEG-2 video decoding.

14. The video decoding system of claim 11 the predetermined addressing patterns allow for reading of the macroblocks needed for decoding the compressed video data from the memory in less clock cycles when compared to sequentially transferring the fixed number of data bytes starting at the fixed address.

16. The video decoding system of claim 9 wherein the addressing patterns include programmable addressing patterns that can change based on data transfer requirements.

17. The video decoding system of claim 9 wherein the compressed video data include at least one of HDTV video data and SDTV video data.

15. A video decoding system comprising:

a video decoder for processing compressed video data to generate displayable video;

a memory controller for transferring the compressed video data to and from a memory; and

a data bus between the video decoder and the memory controller,

wherein the video decoder requests to the memory controller to transfer the compressed video data using one of a plurality of addressing patterns,

wherein the compressed video data includes macroblocks representing MPEG-2 video data, the addressing patterns include predetermined addressing patterns, and the predetermined addressing patterns allow for more efficient transferring of the macroblocks when compared to sequentially transferring a fixed number of data bytes starting at a fixed address, and

wherein the predetermined addressing patterns allow for transferring of the macroblocks needed for decoding the compressed video data over the data bus in less clock cycles as compared to sequentially transferring the fixed number of data bytes starting at the fixed address.

18. A video and graphics system comprising:

a data transport processor for receiving a plurality of transport streams, at least one of the plurality of transport streams including compressed video data;

a video transport processor for extracting the compressed video data from the plurality of transport streams and for storing the compressed video data in an external memory;

a video decoder for decoding the compressed video data to generate decoded video data and for storing the decoded video data in the external memory; and

a memory controller for transferring the compressed video data and the decoded video data in and out of the external memory,

wherein the video decoder uses a plurality of predetermined addressing patterns to request the compressed video data from the memory controller,

wherein the predetermined addressing patterns allow for transferring of the requested compressed video data in less clock cycles as compared to sequentially transferring a fixed number of data bytes starting at a fixed address.

19. The video and graphics system of claim 18 wherein the compressed video data include macroblocks of MPEG-2 video data.

20. The video and graphics system of claim 18 wherein the compressed video data include at least one of HDTV video data and SDTV video data.

21. The video and graphics system of claim 18 wherein the data transport processor, the video transport processor, the video decoder and the memory controller are implemented on an integrated circuit chip.