Dielectric structure

• US 6,661,642 B2
• Filed: 10/10/2002
• Issued: 12/09/2003
• Est. Priority Date: 11/26/2001
• Status: Expired due to Fees

• Current Assignee: Shipley Company, LLC (Dow, Inc.)
• Original Assignee: Shipley Company, LLC (Dow, Inc.)
• Inventors: Cairns, S. Matthew, Rzeznik, Maria Anna, Allen, Craig S.
• Primary Examiner(s): Dinkins, Anthony
• Application Number:
  US10/268,433
• Publication Number:
  US 20030128497A1
• Time in Patent Office: 425 Days
• Field of Search: 361/311, 361/312, 361/313, 361/321.2, 361/321.5, 501/134, 501/135, 501/138, 501/139
• US Class Current: 361/312
• CPC Class Codes: H01G 4/06 Solid dielectrics
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 28/56 the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/0195 Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
• CPC Class Codes: H05K 2201/0236 Plating catalyst as filler in insulating material catalytic ink H05K2203/0709
• CPC Class Codes: H05K 2201/09309 Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 3/181 by electroless plating adhesives therefor H05K3/387

Abstract

Multilayer dielectric structures particularly suitable for use in capacitors and having a plating dopant in an amount sufficient to promote plating of a conductive layer are provided, together with methods of forming such structures. Such dielectric structures show increased adhesion of subsequently applied conductive layers.

Claims

1. A multilayer dielectric structure having a first dielectric layer and a second dielectric layer, wherein the first dielectric layer comprises a plating dopant in an amount sufficient to promote plating of a conductive layer on the first dielectric layer.

2. The multilayer dielectric structure of claim 1 wherein the plating dopant is metallic.

3. The multilayer dielectric structure of claim 1 wherein the plating dopant is present in the first dielectric layer in an amount of up to 50% by volume.

4. The multilayer dielectric structure of claim 1 further comprising a third dielectric layer disposed on the second dielectric layer, wherein the third dielectric layer comprises a plating dopant in an amount sufficient to promote plating of a conductive layer on the third dielectric layer.

5. The multilayer dielectric structure of claim 1 wherein the second dielectric layer comprises a plurality of dielectric layers.

6. A printed circuit board comprising an embedded capacitance material, wherein the embedded capacitance material comprises the multilayer dielectric structure of claim 1.

7. A method of manufacturing a multilayer laminated printed circuit board comprising the step of embedding a capacitance material in one or more layers of a multilayer laminated printed circuit board, wherein the embedded capacitance material comprises the multilayer dielectric structure of claim 1.

8. A dielectric structure having a dielectric layer comprising a plating dopant in an amount sufficient to promote plating of a conductive layer on the dielectric layer.

9. A method of manufacturing a capacitor comprising the steps of depositing on a substrate a dielectric layer comprising plating dopant in an amount sufficient to promote plating of a conductive layer on the first dielectric layer, and plating a conductive layer on the surface of the dielectric layer.

10. The method of claim 9 wherein the plating dopant is metallic.

11. The method of claim 9 wherein the plating dopant is present in the dielectric layer in an amount of up to 50% by volume.

12. The method of claim 9 wherein the substrate comprises a bottom conductive layer and a bottom dielectric layer disposed on the bottom conductive layer.

13. The method of claim 9 wherein the conductive layer is a metal, metal oxide or conductive polymer.

14. A capacitor comprising a dielectric structure having a bottom dielectric layer and a top dielectric layer wherein the top dielectric layer comprises a plating dopant in an amount sufficient to promote plating of a conductive layer on the top dielectric layer, a bottom conductive layer in intimate contact with the bottom dielectric layer and a top conductive layer in intimate contact with the top dielectric layer.

15. The capacitor of claim 14 wherein the plating dopant is metallic.

16. The capacitor of claim 14 wherein the plating dopant is present in the dielectric layer in an amount of up to 50% by volume.

17. The capacitor of claim 14 further comprising a dielectric layer disposed between the top and bottom dielectric layers.

18. The capacitor of claim 17 wherein the bottom dielectric layer comprises a plating dopant in an amount of up to 50% by volume.