PWM controller having adaptive off-time modulation for power saving

• US 6,661,679 B1
• Filed: 10/28/2002
• Issued: 12/09/2003
• Est. Priority Date: 10/28/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: System General Corporation (ON Semiconductor Corporation)
• Inventors: Yang, Ta-yung, Lin, Jenn-yu G.
• Primary Examiner(s): Berhane, Adolf D.
• Application Number:
  US10/065,531
• Time in Patent Office: 407 Days
• Field of Search: 363/21.01, 363/21.1, 363/21.11, 363/21.18, 363/26, 363/41, 363/97
• US Class Current: 363/41
• CPC Class Codes: H01F 2038/026 non-linear inductive arrangements for converters, e.g. with additional windings
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 1/40 Means for preventing magnetic saturation
• CPC Class Codes: H02M 3/33523 with galvanic isolation between input and output of both the power stage and the feedback loop
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

An adaptive off-time modulator of a PWM controller is provided for power saving in the light-load and no-load conditions. The maximum on-time is kept as a constant and a bias current of the oscillator in the PWM controller is moderated to achieve the off-time modulation. Reduction of the bias current increases the off-time of the switching period. The bias current is a function of the supply voltage and the feedback voltage, which is derived from a voltage feedback loop. A threshold voltage defines the level of the light load. A limit voltage defines the low level of the supply voltage. A bias current synthesizer generates the bias current. Once the feedback voltage is decreased lower than the threshold voltage, the bias current is reduced linearly and the off-time of the switching period is increased gradually. When the supply voltage is lower than the limit voltage, the bias current increases and determines a maximum off-time of the switching period. The maximum on-time and off-time of the switching period determines the PWM frequency. As the limit voltage varies in every switching cycle, the frequency spectrum of PWM signal spreads in light-load and no-load conditions; and therefore, the acoustic noise is suppressed. The feedback voltage and the supply voltage determine the switching period of the PWM signal. The maximum on-time is kept constant and the switching period is increased by increasing the off-time, such that the magnetic components, such as inductors and transformers, are prevented from being saturated.

Claims

1. A PWM controller having an adaptive off-time modulator comprising:

a bias current synthesizer having four inputs and one output to generate a bias current that determines an off-time of a PWM switching period;

an oscillator having an input connected to the output of the bias current synthesizer for generating a pulse-signal for PWM switching, wherein a maximum on-time of the pulse-signal, is a constant and an off-time of the pulse-signal is increased as the bias current decreases;

a RS flip-flop generating an on-off signal, wherein the RS flip-flop is set by the pulse-signal and reset by a feedback control;

an AND-gate having two input terminals for outputting a PWM signal, wherein a first input terminal of the AND-gate is connected to the pulse-signal and a second input terminal of the AND-gate connected to the on-off signal;

a feedback voltage connected to a first input of the bias current synthesizer, wherein the feedback voltage is derived from the voltage feedback loop of the power supply for controlling the on-time of the PWM signal and regulating the output of the power supply; and

a threshold voltage is connected to a second input of the bias current synthesizer to determine the level of a light-load condition;

a limit voltage connected to a third input of the bias current synthesizer to determine the level of a low supply voltage;

wherein the limit voltage is changed in every PWM switching cycle which affects the bias current to produce a variable PWM switching frequency when the PWM switching frequency is decreased in the light-load and no-load conditions; and

a supply voltage connected to a fourth input of bias current synthesizer, in which the supply voltage is the power supply voltage of the PWM controller;

wherein the bias current is a function of the feedback voltage, the threshold voltage, the supply voltage, and the limit voltage, such that when the feedback voltage is lower than the threshold voltage, the bias current starts to reduce in response to the decrease of the feedback voltage, and if the supply voltage is lower than the limit voltage, the bias current starts to increase in response to the decrease of the supply voltage.

2. The PWM controller as claimed in claim 1, wherein the bias current synthesizer comprising:

a first adder, operative to subtract the threshold voltage from the feedback voltage;

an attenuator providing the attenuation for the supply voltage;

a second adder, operative to subtract the output of the attenuator from the limit voltage;

a first limiter for scaling and clamping the output of the first adder to a first differential signal, wherein the amplitude of the first differential signal is in the range of zero to a first-maximum;

a second limiter for scaling and clamping the output of the second adder to a second differential signal, in which the amplitude of the second differential signal is in the range of zero to a second-maximum;

a third adder, whereby the first differential signal is added with the second differential signal;

a V-to-I converter for converting the output of the third adder to a V-to-I current;

a third limiter for clamping the V-to-I current to the bias current, in which the amplitude of the bias current is in the range of zero to a current-maximum, wherein the current-maximum determines the minimum off-time of the PWM switching period, the first-maximum determines the slope of the change of the bias current in response to the variation of the feedback voltage, and the second-maximum determines the slope of the change of the bias current in response to the variation of the supply voltage.

3. The PWM controller as claimed in claim 1, wherein the bias current synthesizer comprising:

a first operation amplifier having a positive input, a negative input and an output, in which the positive input is connected to the feedback voltage;

a first buffer amplifier having a positive input, a negative input and an output, in which the negative input is connected to the output and the positive input is connected to the threshold voltage;

a first V-to-I transistor having a gate, a source and a drain, in which the gate is driven by the output of the first operation amplifier, and the source is connected to the negative input of the first operation amplifier developing a first source follow circuit;

a first resistor connected between the output of the first buffer amplifier and the source of the first V-to-I transistor;

wherein the threshold voltage is subtracted from the feedback voltage via the first resistor generating a FB-current;

a divider;

a second operation amplifier having a positive input, a negative input and an output, in which the positive input is connected to the limit voltage;

a second buffer amplifier having a positive input, a negative input and an output, in which the negative input is connected to the output and the positive input is connected to the supply voltage through the divider;

a second V-to-I transistor having a gate, a source and a drain, in which the gate is driven by the output of the second operation amplifier, and the source is connected to the negative input of the second operation amplifier developing a second source follow circuit;

a second resistor connected between the output of the second buffer amplifier and the source of the second V-to-I transistor;

wherein the supply voltage via the divider is subtracted by the limit voltage, and then through the second resistor to generate a VCC-current;

a first-input transistor having a gate, a source and a drain;

a first-output transistor having a gate, a source and a drain, in which the source of the first-input transistor and the source of the first-output transistor are connected together, wherein the drain of the first V-to-I transistor and the drain of the first-input transistor, and the gate of the first-input transistor and the gate of the first-output transistor are connected together to form a first mirror amplifier;

wherein the FB-current drives the first mirror amplifier to generate a first mirror current;

a second-input transistor having a gate, a source and a drain;

a second-output transistor having a gate, a source and a drain, in which the source of the second-input transistor and the source of the second-output transistor are connected together;

wherein the drain of the second V-to-I transistor and the drain of the second-input transistor, and the gate of the second-input transistor and gate of the second-output transistor are connected together to form a second mirror amplifier;

wherein the VCC-current drives the second mirror amplifier to generate a second mirror current; and

a limit current-source connected to the source of the first-input transistor, the source of the first-output transistor, the source of the second-input transistor and the source of the second-output transistor for clamping the maximum output current of the bias current;

wherein the drain of the first-output transistor and the drain of the second-output transistor are connected together to achieve the first mirror current summed with the second mirror current to generate the bias current.

4. The PWM controller as claimed in claim 1, wherein the limit voltage comprising:

a counter for generating the code, in which a clock of the counter is driven by the pulse-signal;

a digital-to-analog converter for generating a variable limit voltage according to the clock of the pulse-signal, wherein the output of the counter drives the digital-to-analog converter; and

a constant reference voltage providing a reference voltage for the digital-to-analog converter.