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Partial selection of passive element memory cell sub-arrays for write operation

  • US 6,661,730 B1
  • Filed: 12/22/2000
  • Issued: 12/09/2003
  • Est. Priority Date: 12/22/2000
  • Status: Expired due to Term
First Claim
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1. An integrated circuit comprising:

  • a memory array comprising a plurality of sub-arrays configured as a plurality M of sub-array groups, each group comprising N sub-arrays, said memory array configured to enable, when writing data into the memory array, fewer sub-array groups than are enabled for reading data from the memory array.

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