Shared peripheral architecture

• US 6,662,253 B1
• Filed: 09/13/2000
• Issued: 12/09/2003
• Est. Priority Date: 09/13/2000
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Tyger, Karen, Gary, Sonya
• Primary Examiner(s): Auve, Glenn A.
• Assistant Examiner(s): VU, TRISHA U
• Application Number:
  US09/660,577
• Time in Patent Office: 1,182 Days
• Field of Search: 710/51, 710/113-125, 710/309, 710/316, 710/317, 710/240-244
• US Class Current: 710/244
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

A disk drive controller including a plurality of processors and a plurality of shared peripheral units. A shared bus couples the peripheral units and the processors. A bi-directional multiplexor selectably couples each of the plurality of processors to the shared bus in response to an owner signal. A set of peripheral-share registers where a first member of the set includes an entry associated with each of the plurality of peripheral units and holds a state value indicating which of the plurality of processors currently owns the associated peripheral unit.

Claims

1. A disk drive controller comprising:

a plurality of processors;

a plurality of peripheral units;

a bus coupling to each of the peripheral units;

a bi-directional multiplexor for selectably coupling each of the plurality of processors to the bus in response to an owner signal;

a set of peripheral-share registers wherein a first member of the set includes an entry associated with each of the plurality of peripheral units that holds a state value indicating which of the plurality of processors currently owns the associated peripheral unit.

2. The controller of claim 1 wherein the multiplexor comprises:

an address multiplexor coupled to address outputs of each of the plurality of processors wherein the address multiplexor selectively couples one of the processor address outputs to a MUX address output based on the state of the owner signal;

a data multiplexor coupled to data outputs of each of the plurality of processors, wherein the data multiplexor selectively couples one of the processor data outputs to a MUX data output based on the state of the owner signal; and

a shared register having an address port coupled to the MUX address output, a data port coupled to the MUX data output, and a bus port coupled to communicate with the bus.

3. The controller of claim 1 wherein the set of peripheral share registers includes a second register holding a value indicating whether the peripheral units are permitted to be dynamically shared amongst the plurality of processors.

4. The controller of claim 1 wherein the set of peripheral share registers includes a plurality of request registers such that each request register corresponds to one of the plurality of processors, wherein each request register has an entry associated with each of the peripheral units, and wherein each entry holds a value indicating whether the corresponding processor is requesting ownership of the associated peripheral unit.

5. The controller of claim 1 wherein the set of peripheral share registers includes a plurality of release registers such that each release register corresponds to one of the plurality of processors, wherein each release resister has an entry associated with each of the peripheral units, and wherein each entry holds a value indicating whether the corresponding processor is releasing ownership of the associated peripheral unit.

6. The controller of claim 1 wherein the set of peripheral share registers includes a priority register having an entry associated with each of the peripheral units, wherein each entry holds a value indicating which of the plurality of processors wins ownership of the associated peripheral unit when a conflict occurs between two or more of the processors requesting ownership of the associated peripheral unit.

8. The controller of claim 1 wherein the state value is dynamically configurable during operation by at least one of the plurality of processors.

7. The controller of clam 1 wherein the state value is set to a static value at boot time.

9. A method for sharing a plurality of peripheral units in a disk drive controller having a plurality of processors comprising:

generating a plurality of access requests using the plurality of processors;

storing a state value associated with each peripheral unit, the state value indicating which of the plurality of processors is a current owner of the associated peripheral; and

selectively coupling each peripheral unit to receive only access requests generated by a particular processor indicated by the state value associated with that peripheral unit.

10. The method of claim 9 further comprising:

performing the storing at boot time as a static value that cannot be changed during operation.

11. The method of claim 9 further comprising:

dynamically altering the state values to create dynamic ownership associations between a peripheral and the plurality of processors.

15. The method of claim 11 further comprising:

storing a priority indication associated with each peripheral unit wherein the priority indication indicates which of the plurality of processors wins ownership when more than one processor generates an access request for the associated peripheral unit at substantially the same time.

12. The method of clam 11 further comprising:

providing a request register for each processor;

providing a release register;

in response to receiving a request for access to a specified peripheral from a first processor, generating an indication in the request register that the first processor has a pending access request;

determining from the state value whether any processor other than the first processor is the current owner of the specified peripheral;

when a second processor owns the peripheral, holding the request in a pending state;

generating an indication in the release register in indicating that the second processor is releasing ownership of the peripheral; and

in response to the indication in the release register, clearing both the request indication and the release indication and changing the state value to indicate that the first processor is the current owner of the specified peripheral.

13. The method of claim 12 wherein the step of providing a request register comprises implementing a data structure for each processor, where each data structure comprises a plurality of entries and each of the entries is associated with a specific one of the plurality of peripheral units.

14. The method of claim 13 wherein the step of providing a release register comprises implementing a data structure for each processor, where each data structure comprises a plurality of entries and each of the entries is associated with a specific one of the plurality of peripheral units.

16. A computer program product embodied in a tangible media and configured to cause a computer to share peripheral units amongst a plurality of host processors, the computer program product comprising:

a first code segment receiving an externally generated access request from a first host processor of the plurality of host processors wherein the access requests specify a peripheral unit;

a second code segment responsive to the first code segment for storing a state value associated with each peripheral unit indicating which of the plurality of processors is a current owner of the associated peripheral; and

a third code segment causing the processor to selectively couple each peripheral unit to receive only access requests generated by a particular processor indicated by the state value associated with that peripheral unit.

17. A multiprocessing computing system comprising:

a plurality of processors;

a plurality of peripheral units, each having a connection to a shared input/output bus;

a bi-directional multiplexor for selectably coupling each of the plurality of processors to the shared input/output bus in response to an owner signal;

wherein the bi-directional multiplexor comprises;

an address multiplexor coupled to address outputs of each of the plurality of processors wherein the address multiplexor selectively couples one of the processor address outputs to a MUX address output based on the state of the owner signal;

a data multiplexor coupled to data outputs of each of the plurality of processors, wherein the data multiplexor selectively couples one of the processor data outputs to a MUX data output based on the state of the owner signal; and

a set of peripheral-share registers wherein a first member of the set includes an entry associated with each of the plurality of peripheral units that holds a state value indicating which of the plurality of processors currently owns the associated peripheral unit.

18. The system of claim 17 wherein the plurality of processors comprise embedded processor cores integrated on a single integrated circuit chip.

19. The system of claim 17 further comprising:

a peripheral control register associated with each of the peripheral units, wherein the peripheral control register is shared amongst the plurality of processors.