Integrated circuits and methods for their fabrication

• US 6,664,129 B2
• Filed: 12/12/2002
• Issued: 12/16/2003
• Est. Priority Date: 10/29/1996
• Status: Expired due to Term

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Tri E Technologies LLC
• Inventors: Siniaguine, Oleg
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): TOLEDO, FERNANDO L
• Application Number:
  US10/318,833
• Publication Number:
  US 20030085460A1
• Time in Patent Office: 369 Days
• Field of Search: 438/629, 438/672, 438/675, 438/458, 438/107, 438/119, 438/667, 438/692, 438/977, 438/FOR.567, 438/FOR.485, 257/E23.011
• US Class Current: 438/107
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/814 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/482 consisting of lead-in layers inseparably applied to the semiconductor body electrodes H01L29/40
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

To fabricate contacts on a wafer backside, openings (124) are formed in the face side of the wafer (104). A dielectric layer (140) and some contact material (150), e.g. metal, are deposited into the openings. Then the backside is etched until the contacts (150C) are exposed and protrude out. The protruding portion of each contact has an outer sidewall (150V). At least a portion of the sidewall is vertical or sloped outwards with respect to the opening when the contact is traced down. The contact is soldered to an another structure (410), e.g. a die or a PCB. The solder (420) reaches and at least partially covers the sidewall portion which is vertical or sloped outwards. The strength of the solder bond is improved as a result. The dielectric layer protrudes around each contact. The protruding portion (140P) of the dielectric becomes gradually thinner around each contact in the downward direction. The thinned dielectric is more flexible, and is less likely detach from the contact when the contact is pulled sideways. Other embodiments are also described.

Claims

1. An integrated circuit fabrication method comprising:

(a) forming one or more openings in a first generally horizontal surface of a semiconductor substrate;

(b) forming a first dielectric and a conductor in each of the one or more openings with the conductor in each of the openings being separated from the substrate by the first dielectric;

(c) removing material from a second generally horizontal surface of the substrate to expose the first dielectric and turn the one or more openings into through holes, and removing the exposed first dielectric to expose the conductor at the second surface of the substrate, such that the first dielectric forms a protrusion at each opening at the second surface, and the conductor protrudes from the first dielectric at each protrusion of the first dielectric;

wherein the protruding portion of each conductor has an outer surface not covered by the dielectric, and at least a portion of the outer surface is either vertical or is sloped outwards, laterally away from the through hole in which the conductor is formed, when the surface is traced in a direction away from the substrate.

2. The method of claim 1 wherein the removing operation (c) comprises a simultaneous etch of the substrate and the first dielectric, such that the first dielectric is etched both vertically and horizontally.

3. The method of claim 1 further comprising attaching the protruding portion of each conductor to a first substrate with a bonding material to form a conductive bond between the conductor and the first substrate, wherein the bonding material reaches and at least partially covers said outer surface portion which is either vertical or sloped outwards.

4. The method of claim 3 wherein the bonding material comprises solder which bonds the conductor to the first substrate, wherein the solder reaches and at least partially covers said outer surface portion which is either vertical or sloped outwards.

5. The method of claim 3 wherein said portion of the protruding outer surface of the conductor is sloped outwards.

6. The method of claim 1 wherein:

forming the conductor comprises forming a first conductive layer and a second conductive layer separating the first conductive layer from the dielectric;

wherein the method further comprises removing the second conductive layer during and/or after the operation (c) to expose the first conductive layer at the bottom of the substrate.

7. The method of claim 6 wherein the first conductive layer is solder wettable, and the second conductive layer is not solder wettable.

8. An integrated circuit fabrication method comprising:

forming one or more openings in a top surface of a semiconductor substrate, wherein each opening has a sidewall, and at least a first portion of the sidewall is either vertical or sloped outwards relative to the opening when the sidewall is traced down;

forming a first dielectric and a conductor in each opening with the conductor in each opening being separated from the substrate by the first dielectric;

removing material from a bottom surface of the substrate to expose the first dielectric and turn the one or more openings into through holes, and removing the exposed first dielectric to expose the conductor at the bottom surface of the substrate, such that the first dielectric forms a protrusion at each opening at the bottom surface, and the conductor protrudes from the first dielectric at each protrusion of the first dielectric;

wherein the removing operation (c) removes the semiconductor material from said first portion of the sidewall of each opening, and removes the dielectric adjacent to the first sidewall portion of the opening, to expose the conductor adjacent to the first sidewall portion of the opening.

9. The method of claim 8 wherein the removing operation (c) comprises a simultaneous etch of the substrate and the first dielectric, such that the first dielectric is etched both vertically and horizontally.

10. The method of claim 8 further comprising attaching the protruding portion of each contact to a first substrate with a bonding material which reaches and at least partially covers said exposed conductor which was adjacent to the first sidewall portion of each opening.

11. The method of claim 10 wherein the bonding material comprises solder which bonds the conductor to the first substrate, wherein the solder reaches and at least partially covers said outer surface portion which is either vertical or sloped outwards.

12. The method of claim 10 wherein said portion of the protruding outer surface of the conductor is sloped outwards;

and

the bonding material is anisotropic adhesive.

13. The method of claim 8 wherein:

forming the conductor comprises forming a first conductive layer and a barrier layer preventing intermixing between the first conductive layer and the dielectric;

wherein the method further comprises removing the barrier layer during and/or after the operation (c) to expose the first conductive layer at the bottom of the substrate.

14. The method of claim 13 wherein the first conductive layer is solder wettable, and the second conductive layer is not solder wettable.

15. An integrated circuit fabrication method comprising:

forming one or more openings in a first surface of a semiconductor substrate;

forming a dielectric and a conductor in each of the one or more openings with the conductor in each of the openings being separated from the substrate by the dielectric;

removing material from a second surface of the substrate to expose the dielectric and turn the one or more openings into through holes, and removing the exposed dielectric to expose the conductor at the second surface of the substrate, such that at each through hole the dielectric forms a protrusion around the conductor at the second surface;

wherein the removing operation comprises a simultaneous etch of the substrate and the first dielectric, such that the first dielectric is etched both vertically and horizontally.

16. The method of claim 15 wherein the conductor protrudes from the dielectric at each protrusion of the dielectric.

17. The method of claim 16 further comprising soldering the protruding portion of each conductor to a first substrate.