Methods of fabricating vertical field effect transistors by conformal channel layer deposition on sidewalls

• US 6,664,143 B2
• Filed: 11/06/2001
• Issued: 12/16/2003
• Est. Priority Date: 11/22/2000
• Status: Expired due to Fees

• Current Assignee: North Carolina State University (University of North Carolina System)
• Original Assignee: North Carolina State University (University of North Carolina System)
• Inventors: Zhang, Zhibo
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US10/007,895
• Publication Number:
  US 20020060338A1
• Time in Patent Office: 770 Days
• Field of Search: 438/212, 438/268, 438/259, 438/270, 438/271, 438/587, 438/588, 438/589, 438/138, 257/328, 257/329, 257/330, 257/331
• US Class Current: 438/138
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

Vertical field effect transistors are fabricated by depositing a vertical channel on a microelectronic substrate at a thickness along the microelectronic substrate that is independent of lithography, the vertical channel extending orthogonal to the microelectronic substrate. Source and drain regions are formed at respective opposite ends of the vertical channel, and an insulated gate is formed adjacent the vertical channel. More specifically, a first doping layer is formed on a microelectronic substrate, an intermediate layer is formed on the first doping layer opposite the substrate and a second doping layer is formed on the intermediate layer opposite the first doping layer. A trench is then formed in the first doping layer, the intermediate layer and the second doping layer, the trench including a trench sidewall. The trench sidewall is lined with a conformal amorphous silicon layer. The conformal silicon layer on the trench sidewall includes a first end portion adjacent the first doping layer, a second end portion adjacent the second doping layer, and a middle portion between the first and second end portions adjacent the intermediate layer. The amorphous silicon layer is then crystallized. The trench that is lined is plugged, for example with high dielectric constant material. Annealing is performed to dope the first end portion and the second end portion with dopants from the first and second doping layers respectively. The intermediate layer is removed adjacent the middle portion to expose at least some of the middle portion. A gate insulating layer is formed on the middle portion that is exposed, and a gate electrode is formed on the gate insulating layer, opposite the middle portion. One or more drain contacts may be formed in the microelectronic substrate prior to forming the first doping layer, for example using silicide. Moreover, one or more source contacts may be formed on the second end of the conformal silicon layer.

Claims

1. A method of fabricating a vertical field effect transistor comprising:

depositing a vertical channel on a microelectronic substrate at a thickness along the microelectronic substrate that is independent of lithography, the vertical channel extending orthogonal to the microelectronic substrate;

then

forming source and drain regions at respective opposite ends of the vertical channel; and

then

forming an insulated gate adjacent the vertical channel.

2. A method according to claim 1 wherein the forming an insulated gate adjacent the vertical channel comprises:

forming an insulating layer on the vertical channel, the insulating layer extending orthogonal to the microelectronic substrate and having a length along the channel that is independent of lithography; and

forming a gate electrode on the insulating layer opposite the vertical channel, the gate electrode having a length along the channel that is independent of lithography.

3. A method according to claim 2:

wherein the forming an insulating layer is preceded by forming a layer of predetermined thickness on the microelectronic substrate that extends adjacent the vertical channel;

wherein the forming an insulating layer comprises forming an insulating layer on the vertical channel that extends orthogonal to the microelectronic substrate and that has a length along the channel that is determined by the predetermined thickness; and

wherein the forming a gate electrode comprises forming a gate electrode on the insulating layer opposite the vertical channel and that has a length along the channel that is determined by the predetermined thickness.

4. A method of fabricating a vertical field effect transistor comprising:

lining a sidewall of a trench on a microelectronic substrate with a conformal silicon layer, the conformal silicon layer on the sidewall of the trench including a first end portion adjacent the substrate, a second end portion remote from the substrate and a middle portion between the first and second end portions;

then

doping the first and second end portions to form source and drain regions for the field effect transistor;

then

forming a gate insulating layer adjacent the middle portion; and

then

forming a gate electrode on the gate insulating layer opposite the middle portion.

5. A method according to claim 4 wherein the lining a sidewall of a trench comprises:

lining the sidewall of the trench with amorphous silicon; and

crystallizing the amorphous silicon.

6. A method according to claim 5 wherein the lining the sidewall of a trench is followed by plugging the trench that is lined.

7. A method according to claim 6 wherein the plugging comprises plugging the trench that is lined with a high dielectric constant dielectric.

8. A method according to claim 4 wherein the lining the sidewall of a trench comprises lining the entire sidewall of the trench to provide a continuous conformal silicon layer.

9. A method according to claim 4 wherein the lining the sidewall of a trench comprises lining spaced apart portions of the trench sidewall with the conformal silicon layer to provide spaced apart conformal silicon plates.

10. A method according to claim 4 wherein the lining the sidewall of a trench is preceded by:

forming a first layer on the substrate;

forming an intermediate layer on the first layer opposite the substrate;

forming a second layer on the intermediate layer opposite the first layer; and

defining the trench in the first layer, the intermediate layer and the second layer.

11. A method according to claim 10 wherein the lining the sidewall of a trench comprises:

lining the sidewall of the trench with the conformal silicon layer, the conformal silicon layer on the sidewall of the trench including the first and second end portions adjacent the first and second layers, respectively, and the middle portion adjacent the intermediate layer.

12. A method of fabricating a vertical field effect transistor comprising:

lining a sidewall of a trench on a microelectronic substrate with a conformal silicon layer, the conformal silicon layer on the sidewall of the trench including a first end portion adjacent the substrate, a second end portion remote from the substrate and a middle portion between the first and second end portions;

doping the first and second end portions to form source and drain regions for the field effect transistor;

forming a gate insulating layer adjacent the middle portion; and

forming a gate electrode on the gate insulating layer opposite the middle portion;

wherein the lining the sidewall of a trench is preceded by;

forming a first doping layer on the substrate;

forming an intermediate layer on the first doping layer opposite the substrate;

forming a second doping layer on the intermediate layer opposite the first doping layer; and

defining the trench in the first doping layer, the intermediate layer and the second doping layer.

13. A method according to claim 12 wherein the lining the sidewall of a trench comprises:

lining the sidewall of the trench with the conformal silicon layer, the conformal silicon layer on the sidewall of the trench including the first end portion adjacent the first doping layer, the second end portion adjacent the second doping layer and the middle portion adjacent the intermediate layer.

14. A method according to claim 13 wherein the doping comprises doping the first and second end portions with dopants from the respective first and second doping layers adjacent thereto, to form source and drain regions for the field effect transistor.

15. A method according to claim 14 wherein the forming a gate insulating layer adjacent the middle portion comprises:

removing the intermediate layer adjacent the middle portion to expose at least some of the middle portion; and

forming a gate insulating layer on the middle portion that is exposed.

16. A method according to claim 15 wherein the forming a gate insulating layer on the middle portion that is exposed comprises thermally oxidizing the middle portion that is exposed.

17. A method according to claim 12 wherein the first and second doping layers comprise phosphosilicate glass and/or borosilicate glass.

18. A method according to claim 12:

wherein the forming a first doping layer is preceded by forming a silicide layer on the substrate; and

wherein the forming a first doping layer comprises forming a first doping layer on the silicide layer opposite the substrate.

19. A method of fabricating a vertical field effect transistor comprising:

lining a sidewall of a trench on a microelectronic substrate with a conformal silicon layer, the conformal silicon layer on the sidewall of the trench including a first end portion adjacent the substrate, a second end portion remote from the substrate and a middle portion between the first and second end portions;

doping the first and second end portions to form source and drain regions for the field effect transistor;

forming a gate insulating layer adjacent the middle portion; and

forming a gate electrode on the gate insulating layer opposite the middle portion;

wherein the lining the sidewall of a trench comprises;

lining the sidewall of the trench with the conformal silicon layer, the conformal silicon layer on the sidewall of the trench including the first and second end portions adjacent the first and second layers, respectively, and the middle portion adjacent the intermediate layer; and

wherein the forming a gate insulating layer adjacent the middle portion comprises;

removing the intermediate layer adjacent the middle portion to expose at least some of the middle portion; and

forming a gate insulating layer on the middle portion that is exposed.

20. A method according to claim 19 wherein the forming a gate insulating layer on the middle portion that is exposed comprises thermally oxidizing the middle portion that is exposed.

21. A method of fabricating a vertical field effect transistor comprising:

forming a first doping layer on a microelectronic substrate;

forming an intermediate layer on the first doping layer opposite the substrate;

forming a second doping layer on the intermediate layer opposite the first doping layer;

forming a trench in the first doping layer, the intermediate layer and the second doping layer, the trench including a trench sidewall;

lining the trench sidewall with a conformal amorphous silicon layer, the conformal amorphous silicon layer on the trench sidewall including a first end portion adjacent the first doping layer, a second end portion adjacent the second doping layer and a middle portion between the first and second end portions adjacent the intermediate layer;

crystallizing the amorphous silicon layer;

plugging the trench that is lined;

annealing to dope the first end portion and the second end portion with dopants from the first and second doping layers, respectively;

removing the intermediate layer adjacent the middle portion to expose at least some of the middle portion;

forming a gate insulating layer on the middle portion that is exposed; and

forming a gate electrode on the gate insulating layer, opposite the middle portion.

22. A method according to claim 21 wherein the first and second doping layers comprise phosphosilicate glass and/or borosilicate glass.

23. A method according to claim 21 wherein the plugging comprises plugging the trench with an oxide plug.

24. A method according to claim 21 wherein the plugging comprises plugging the trench with a plug that comprises high dielectric constant material.

25. A method according to claim 21 wherein the lining the sidewall of a trench comprises lining the entire sidewall of the trench to provide a continuous conformal amorphous silicon layer.

26. A method according to claim 21 wherein the lining the sidewall of a trench comprises lining spaced apart portions of the trench sidewall to provide spaced apart conformal amorphous silicon plates.

27. A method according to claim 21 wherein the forming a gate insulating layer on the middle portion that is exposed comprises thermally oxidizing the middle portion that is exposed.

28. A method according to claim 21 wherein the forming a first doping layer on a microelectronic substrate is preceded by forming a drain contact in the microelectronic substrate and wherein the forming a first doping layer comprises a first doping layer on the microelectronic substrate adjacent the drain contact.

29. A method according to claim 28 wherein the drain contact comprises silicide.

30. A method according to claim 21 further comprising forming a source contact on the second end portion.