Method for forming L-shaped spacers with precise width control

• US 6,664,156 B1
• Filed: 07/31/2002
• Issued: 12/16/2003
• Est. Priority Date: 07/31/2002
• Status: Active Grant

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Lin, Wenhe, Ang, Chew Hoe, Lim, Eng Hua, Zheng, Jia Zhen
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): GARCIA, JOANNIE A
• Application Number:
  US10/209,573
• Time in Patent Office: 503 Days
• Field of Search: 438/201, 438/211, 438/229, 438/230, 438/299, 438/303, 438/479, 438/492, 438/696, 438/703, 438/738, 438/743, 438/FOR.188
• US Class Current: 438/229
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method of fabrication of L-shaped spacers in a semiconductor device. A gate structure is provided over a substrate. We form a first dielectric layer over the gate dielectric layer and the substrate. Next, a second dielectric layer is formed over the first dielectric layer. Then, we form a third dielectric layer over the second dielectric layer. The third dielectric layer is anisotropically etched to form a disposable spacer on the second dielectric layer. The second dielectric layer and the first dielectric layer are anisotropically etched using the disposable spacer as a mask to form a top and a bottom L-shaped spacer. The disposable spacer is removed. In preferred embodiments, the first, second and third dielectric layers are formed by atomic layer deposition (ALD) or ALCVD processes.

Claims

1. A method of fabrication of L-shaped spacers in a semiconductor device, comprising the steps of:

a) providing a gate structure over a substrate;

b) forming a first dielectric layer over said gate structure and said substrate;

said first dielectric layer formed using an atomic layer deposition process;

c) forming a second dielectric layer over said first dielectric layer;

said second dielectric layer formed using an atomic layer deposition process;

d) forming a third dielectric layer over said second dielectric layer;

said third dielectric layer formed using an atomic layer deposition process;

the steps of forming said first dielectric layer, said second dielectric layer and said third dielectric layer are performed in-situ using an atomic layer chemical vapor deposition process;

e) etching said third dielectric layer to form a disposable spacer on said second dielectric layer;

f) anisotropically etching said second dielectric layer and said first dielectric layer using said disposable spacer as a mask to form a top and a bottom L-shaped spacer; and

g) removing said disposable spacer.

2. The method of claim 1 wherein at least two gate structures are provided;

and top and bottom L-shaped spacers are formed on said gate structures;

a space between adjacent gate structures is between 0.01 μ

m to 0.9 μ

m.

3. The method of claim 1 wherein said first dielectric layer is comprised of silicon oxide, said second dielectric layer is comprised of aluminum oxide, and said third dielectric layer is comprised of silicon oxide.

4. The method of claim 1 wherein said first dielectric layer is comprised of a material selected from the group consisting of hafnium oxide and zirconium oxide, said second dielectric layer is comprised of silicon oxide;

and said third dielectric layer is a material selected from the group consisting of hafnium oxide and zirconium oxide.

5. The method of claim 1 wherein said first dielectric layer is comprised of a material selected from the group consisting of hafnium oxide and zirconium oxide, said second dielectric layer is comprised of aluminium oxide;

and said third dielectric layer is comprised of a material selected from the group consisting of hafnium oxide and zirconium oxide.

6. The method of claim 1 wherein the steps of forming said first dielectric layer, said second dielectric layer and said third dielectric layer are performed in-situ using an atomic layer deposition (ALD) process in the same chamber;

said first dielectric layer has thickness between 50 and 200 Å

, said second dielectric layer has a thickness between 130 and 300 Å and

said third dielectric layer has a thickness between 300 and 700 Å

.

7. The method of claim 1 which farther includes before the step of forming said first dielectric layer,

forming lightdoped source and drain regions adjacent said gate structure in said substrate.

8. The method of claim 1 which further includes:

forming source and drain regions adjacent to said top and bottom L-shaped spacers and forming a pocket implant in said substrate.

9. The method of claim 1 wherein said gate structure comprised of a gate dielectric layer and an overlying gate;

said gate dielectric layer is comprised of silicon oxide;

said gate dielectric layer has a thickness between 8 and 50 Å

;

said gate is comprised of polysilicon, said gate has a width of between about 0.01 and 2 μ

m and said gate has a height between about 1000 and 3000 Å

.

10. The method of claim 1 wherein said first dielectric layer is comprised of a material selected from the group consisting of oxide, hafnium oxide (HfO₂), and zirconium oxide (ZrO₂), said first layer has a thickness of between about 50 and 200 Å

;

said first dielectric layer formed at a temperature below 500°

C.

11. The method of claim 1 wherein said third dielectric layer formed by an atomic layer deposition (ALD) process using tetraisocyanatesilane (TICS) and water;

said third dielectric layer comprised of oxide, said third dielectric layer formed at a temperature between 200 and 400°

C.

12. The method of claim 1 wherein said third dielectric layer formed by an atomic layer deposition (ALD) process, said third dielectric layer comprised of a material selected from the group consisting of:

oxide, hafnium oxide, and zirconium oxide;

said third dielectric layer formed at a temperature between 200 and 400°

C.

13. The method of claim 1 wherein said disposable spacer has a width of between about 300 and 700 Å

and a height between about 50 and 1500 Å

.

14. The method of claim 1 wherein said gate structure and said semiconductor device have a design rule less than 0.1 μ

m.

15. A method of fabrication of L-shaped spacers in a semiconductor device, comprising the steps of:

a) providing a gate structure over a substrate;

b) forming a firs dielectric layer over said gate structure and said substrate;

said first dielectric layer formed using an atomic layer deposition process;

said first dielectric layer formed by an atomic layer deposition process using tetraisocyanatesilane and water, and said first dielectric layer comprised of oxide;

said first dielectric layer has a thickness of between about 50 and 200 Å

;

said first dielectric layer formed at a temperature between about 200 and 400°

C.;

c) forming a second dielectric layer over said first dielectric layer;

said second dielectric layer formed using an atomic layer deposition process;

d) forming a third dielectric layer over said second dielectric layer;

said third dielectric layer formed using an atomic layer deposition process;

e) etching said third dielectric layer to form a disposable spacer on said second dielectric layer,

f) anisotropically etching said second dielectric layer and said first dielectric layer using said disposable spacer as a mask to form a top and a bottom L-shaped spacer, and

g) removing said disposable spacer.

16. A method of fabrication of L-shaped spacers in a semiconductor device, comprising the steps of:

a) providing a gate structure over a substrate;

b) forming a first dielectric layer over said gate structure and said substrate;

said first dielectric layer formed using an atomic layer deposition process;

c) forming a second dielectric layer over said first dielectric layer;

said second dielectric layer formed using an atomic layer deposition process;

said second dielectric layer is formed by an atomic layer deposition (ALD) process using trimethyaluminum (TMA) and ozone and water and said second dielectric layer comprised of aluminum oxide, said second dielectric layer formed at a temperature between 400 and 450°

C.;

d) forming a third dielectric layer over said second dielectric layer;

said third dielectric layer formed using an atomic layer deposition process;

e) etching said third dielectric layer to form a disposable spacer on said second dielectric layer;

f) anisotropicly etching said second dielectric layer and said first dielectric layer using said disposable spacer as a mask to form a top and a bottom L-shaped spacer, and

g) removing said disposable spacer.

17. A method of fabrication of L-shaped spacers in a semiconductor device, comprising the steps of:

a) providing a gate structure over a substrate;

b) forming a first dielectric layer over said gate structure and said substrate;

said first dielectric layer formed using an atomic layer deposition process;

c) forming a second dielectric layer over said first dielectric layer;

said second dielectric layer formed using an atomic layer deposition process;

d) forming a third dielectric layer over said second dielectric layer, said third dielectric layer formed using an atomic layer deposition process;

said third dielectric layer formed by an atomic layer deposition process using tetraisocyanatesilane and water;

said third dielectric layer comprised of oxide, said third dielectric layer formed at a temperature between 200 and 400°

C.;

e) etching said third dielectric layer to form a disposable spacer on said second dielectric layer;

f) anisotropically etching said second dielectric layer and said first dielectric layer using said disposable spacer as a mask to form a top and a bottom L-shaped spacer; and

g) removing said disposable spacer.