Low on-resistance trench lateral MISFET with better switching characteristics and method for manufacturing same

• US 6,664,163 B2
• Filed: 11/13/2001
• Issued: 12/16/2003
• Est. Priority Date: 12/05/1997
• Status: Expired due to Term

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Device Technology Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Fujishima, Naoto, Salama, C. Andre T.
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): BROPHY, JAMIE LYNN
• Application Number:
  US10/007,081
• Publication Number:
  US 20020113263A1
• Time in Patent Office: 763 Days
• Field of Search: 438/259, 438/268, 438/270, 438/589, 438/FOR.197
• US Class Current: 438/270
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A high-voltage and low on-resistance semiconductor device incorporates a trench structure that provides improved switching characteristics. In a preferred embodiment, a Trench Lateral Power MISFET is provided having a gate, channel and drift regions that are built on the side-walls of the trench. The process used to form the MISFET involves a self-aligned trench bottom contact hole to contact a source provided at the bottom of the trench to achieve minimum pitch and very low on-resistance. An example of a MISFET with 80 V breakdown voltage having a cell pitch of 3.4 microns is disclosed in which an on-resistance of 0.7 mΩ-cm² is realized. The switching characteristics of the MISFET are twice as good as that of prior MISFET device structures.

Claims

1. A method of manufacturing a MISFET comprising the steps of:

a) forming a trench in a substrate of first conductive type;

b) forming a first region of the first conductivity type and a second region of the second conductivity type into the substrate through portions of the trench;

c) depositing an oxide layer on portions of sidewalls of the trench, wherein said oxide layer extends from the top of the trench;

d) then forming an extended trench while retaining said oxide layer on the portions of the sidewalls of said trench;

e) forming a gate oxide layer on the sidewalls of said extended trench;

f) forming a gate layer on the gate oxide layer;

selectively etching the gate layer, and the gate oxide layer so that the surface of the substrate is exposed in regions adjacent to the trench and residual films of the gate layer and the gate oxide layer are left on the sidewalls of the trench;

g) forming a base of the first conductivity type and a source of the second conductivity type at the bottom of the trench;

h) forming a second oxide layer inside the trench and on the surface of the substrate over a drain by a method where oxide growth rate is slower inside the trench than at the surface of the substrate, wherein the thickness of the second oxide layer within the trench is less than the thickness of the second oxide layer on the surface of the substrate;

i) etching the oxide layer at the bottom of the trench to form a contact hole that extends to the substrate while maintaining a thickness of the second oxide layer on the sidewalls of the trench and surface of the substrate using a directional etching method; and

j) forming an electrical interconnection material in the trench that extends through the contact hole.

2. A method of manufacturing an MISFET comprising:

a) selectively forming a second conductivity type diffusion layer in a surface region of a first conductivity type silicon substrate;

b) forming a first trench in the silicon substrate;

c) forming a first conductivity body and a second conductivity drain region in the silicon substrate by implantation through side walls of the first trench;

d) forming a thick oxide layer in the first trench and on the surface of the silicon substrate;

e) then etching through the thick oxide layer and into the silicon substrate to form a second trench;

d) forming a gate oxide layer in the second trench;

e) depositing a polysilicon layer over the gate oxide layer and the thick oxide layer;

f) forming a top oxide layer and selectively etching the top oxide layer to define a gate area;

g) etching the polysilicon layer using the top oxide layer as a mask;

h) forming a first conductivity type base region in the silicon substrate under the bottom of the second trench;

i) depositing an oxide layer in the second trench, wherein the oxide inside the second trench is thinner than that at the surface of the silicon substrate;

j) forming a contact hole at the bottom of the second trench;

k) filling the contact hole with polysilicon; and

l) opening contact windows in the polysilicon and filling the contact holes with metal.