Method and apparatus for lead-frame based grid array IC packaging

• US 6,664,615 B1
• Filed: 11/20/2001
• Issued: 12/16/2003
• Est. Priority Date: 11/20/2001
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Poddar, Anindya, Bayan, Jaime
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): GREENE, PERSHELLE L
• Application Number:
  US09/990,083
• Time in Patent Office: 756 Days
• Field of Search: 257/737, 257/738, 257/734, 257/786, 257/784, 257/778, 257/678, 257/668, 257/698, 257/692, 257/693, 257/641, 257/690, 257/696, 257/676, 257/666, 257/787
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Integrated circuit (IC) package structures and IC package fabrication techniques are provided. The IC package substrate is formed from a metal sheet that is patterned to form a substrate with pads and leads. These pads and leads are pattered throughout the substrate including at least part of the die mounting area. The die is mounted onto the die mounting area of the lead-frame, and respective bonding terminals on the die are electrically connected to the associated bonding areas on the patterned leads. A protective encapsulant is molded to cover the die, bond wires, and most, if not all, of the patterned substrate. Contacts for external electrical connection are formed onto the bottom of the pads.

Claims

1. An integrated circuit package comprising:

a lead-frame having a die mounting area and a multiplicity of bonding locations, the lead frame being patterned to form a plurality of leads and contact pads, wherein at least some of the contact pads are formed within the die mounting area;

a die having a multiplicity of I/O pads, wherein the die is carried by the die mounting area of the lead frame;

a plurality of electrically conductive connections connecting the respective I/O pads on said die to bonding locations on the lead-frame;

an encapsulant that covers the die and at least a portion of the lead-frame, wherein at least a portion of the lead-frame is left exposed, the exposed lead-frame including at least one exposed contact pad.

2. An integrated circuit package as recited in claim 1 further comprising an adhesive between the die and patterned lead-frame.

3. An integrated circuit package as recited in claim 2 wherein the adhesive is a programmable epoxy resin.

4. An integrated circuit package as recited in claim 1 further comprising an electromagnetic shield in or on the encapsulant, the shield covering at least part of the lead-frame, the shield being electrically connected to at least one of the patterned leads.

5. An integrated circuit package as recited in claim 1 further comprising a dielectric that covers at least part of the exposed patterned lead-frame.

6. An integrated circuit package as recited in claim 1 wherein solder balls or plates are formed on the at least one exposed contact pad.

7. An electronic module comprising:

a printed circuit board; and

an integrated circuit package as recited in claim 1, wherein the printed circuit board carries the integrated circuit package.

8. A panel assembly suitable for use in packaging a plurality of integrated circuits, the panel assembly comprising:

a lead frame panel formed from a conductive sheet, the lead frame panel being patterned to define a plurality of adjacent device areas, each device area being suitable for use as the lead-frame of an integrated circuit package as recited in claim 1.

9. A lead frame for use in an integrated circuit package, the lead frame comprising a multiplicity of leads, wherein at least a plurality of the leads have contact pads integrally formed therewith that are suitable for forming exposed external contacts, the contact pads having a larger width or diameter than an immediately adjacent portion of the associated leads, the lead frame further including a die mounting area wherein at least one of the contact pads is positioned within the die mounting area.

10. A panel assembly suitable for use in packaging a plurality of integrated circuits, the panel assembly comprising:

a lead frame panel formed from an electrically conductive sheet, the lead frame panel being patterned to define a plurality of device areas, each device area being suitable for use as the lead-frame recited in claim 9.

11. The panel assembly as recited in claim 10, wherein the plurality of device areas comprise a two dimensional array of immediately adjacent device areas.

12. The panel assembly as recited in claim 10, further comprising:

a plurality of integrated circuits mounted on associated die mounting areas, the integrated circuits each having a plurality of I/O pads;

a plurality of bonding wires that electrically interconnect I/O pads on the integrated circuits and associated bonding locations on the lead-frame panel; and

an encapsulant that covers the integrated circuits and bonding wires and at least a portion of the lead-frame while leaving a bottom surface of the lead-frame at least partially exposed.

13. The panel assembly as recited in claim 12, further comprising:

a patterned dielectric covering at least a part of the exposed lead-frame surface, wherein the dielectric patterning leaves exposed at least some portion of the contact pads; and

least one contact electrically coupled to at least one of the exposed contact pads, whereby the contacts may be used to electrically couple electrical devices to the patterned leads.

14. A method to make a lead-frame suitable for semiconductor packaging comprising the steps of:

patterning an electrically conductive sheet, the patterning forms at least one device region having leads and contact pads, the device region further having a die mounting area, wherein the die mounting area includes at least one contact pad.

15. The method to make a lead-frame assembly comprising the steps of:

attaching at least one die to associated die mounting areas in the lead-frame formed as recited in claim 14, the die having a plurality of I/O bond pad; and

electrically connecting die I/O bond pads to leads in the device region.

16. The method recited in claim 15, wherein the die is attached by a programmable epoxy resin.

17. The method of making semiconductor packaging comprising the steps of:

molding an encapsulant over the lead-frame assembly formed as recited in claim 15, wherein the encapsulant covers the die, the electrical connections and at least a portion of the patterned device region, leaving a surface of the sheet at least partially exposed.

18. The method recitied in claim 17, wherein a shielding area is formed in or on the encapsulant, the shield covering at least part of the die, wherein the shielding area is electrically connected to at least one of the patterned leads to provide at least partial electromagnetic shielding to the die or its electrically conductive connections.

19. The method recited in claim 17, further comprising the steps of:

patterning a dielectric to cover at least a part of the exposed lead-frame surface, wherein the dielectric patterning leaves exposed at least some portion of the contact pads; and

forming a multiplicity of electrically conductive contact on the exposed contact pads, whereby the contacts may be used to electrically couple electrical devices to the patterned leads.

20. The method recited in claim 19, further comprising the steps of:

singulating the device regions into individual semiconductor packages.

21. A packaged semiconductor device comprising:

a conductive lead-frame having a die mounting area, the lead frame being patterned to form a plurality of leads and a plurality of contact pads, wherein at least some of the contact pads are formed within the die mounting area;

a die having a multiplicity of I/O pads, wherein the die is carried by the die mounting area of the lead frame;

a plurality of conductors arranged to electrically connect the respective I/O pads on said die to associated leads in the lead-frame;

an encapsulant that covers the die and at least a portion of the lead-frame, wherein at least the contact pad portions of the lead-frame are left exposed.

22. A panel assembly suitable for use in an integrated circuit packaging, the panel assembly comprising:

a lead frame panel patterned to define at least one two dimensional array of substantially immediately adjacent device areas, wherein each device areas includes a plurality of leads and a plurality of contact pads;

a plurality of dice, each die being mounted on an associated device area, the die being mounted over at least some of the contact pads and electrically connected to associated leads in the associated device area; and

at least one encapsulant cap that covers an associated two dimensional array of immediately adjacent device areas while leaving the contact pads exposed, whereby at least some of the exposed lead frame contact pads are located below the dice.