Utilization of die active surfaces for laterally extending die internal and external connections

• US 6,664,632 B2
• Filed: 01/15/2003
• Issued: 12/16/2003
• Est. Priority Date: 01/13/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M., Duesman, Kevin G.
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US10/345,895
• Publication Number:
  US 20030127662A1
• Time in Patent Office: 335 Days
• Field of Search: 257/750, 257/758, 257/751, 257/778, 257/690, 257/691
• US Class Current: 257/750
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with external communication traces which are used to route signals from the flip-chip integrated circuitry. Such external communication traces generally result in unused space on the exterior surface of the flip-chip. This unused space can be utilized for forming routing traces to connect portions of the internal circuitry of the flip-chip rather than forming such routing traces internally, for forming routing traces to connect two or more semiconductor dice, or for forming routing traces for use as repair mechanisms.

Claims

1. A semiconductor device, comprising:

a semiconductor chip including at least one active surface comprising internal circuitry;

a plurality of conductive elements over the at least one active surface for directing signals between the internal circuitry of the semiconductor chip and at least one other component external to the semiconductor chip; and

at least one routing trace extending over an area of the at least one active surface unoccupied by the conductive elements to connect a first internal circuit component to a second internal circuit component of the semiconductor chip.

2. The semiconductor device of claim 1, wherein the area of the at least one active surface unoccupied by the conductive elements extends substantially an entire length of the semiconductor chip.

3. The semiconductor device of claim 1, wherein at least one of the at least one routing trace is configured to interconnect at least two otherwise electrically isolated internal circuitry components of the semiconductor chip.

4. The semiconductor device of claim 3, wherein the at least two otherwise electrically isolated internal circuitry components lie substantially within a same plane, and further comprising a third internal circuit component disposed between the at least two otherwise electrically isolated internal circuitry components.

5. The semiconductor device of claim 1, wherein at least one of the at least one routing trace is a component of a first circuit of the internal circuitry, and wherein the first circuit is redundant with at least one second circuit of the internal circuitry.

6. The semiconductor device of claim 5, wherein the at least one second circuit of the internal circuitry is configured to be activated when the at least one of the at least one routing trace is severed.

7. The semiconductor device of claim 5, wherein the at least one second circuit of the internal circuitry is configured to be deactivated when the at least one of the at least one routing trace is severed.

8. The semiconductor device of claim 1, wherein the semiconductor chip is configured as a memory chip.

9. A semiconductor device, comprising:

a semiconductor chip including at least one active surface comprising internal circuitry;

a plurality of conductive elements over the at least one active surface for directing signals between the internal circuitry of the semiconductor chip and at least one other component external to the semiconductor chip; and

at least one routing trace carried over an area of the at least one active surface unoccupied by the conductive elements, the at least one routing trace comprising a repair mechanism.

10. The semiconductor device of claim 9, wherein the repair mechanism is configured to be operable by severance of the at least one routing trace to activate a selected internal circuit in the semiconductor chip.

11. The semiconductor device of claim 10, wherein the at least one routing trace is a component of a first circuit of the internal circuitry, and wherein the first circuit is redundant with the selected internal circuit.

12. The semiconductor device of claim 9, wherein the repair mechanism is configured to be operable by severance of the at least one routing trace to deactivate a selected internal circuit in the semiconductor chip.

13. The semiconductor device of claim 12, wherein the at least one routing trace is a component of a first circuit of the internal circuitry, and wherein the first circuit is redundant with the selected internal circuit.

14. The semiconductor device of claim 9, wherein the semiconductor chip is configured as a memory chip.

15. A semiconductor device, comprising:

a semiconductor chip including at least one active surface comprising internal circuitry;

a plurality of conductive elements over the at least one active surface for directing signals between the internal circuitry of the semiconductor chip and at least one other component external to the semiconductor chip; and

at least one routing trace carried over an area of the at least one active surface and lying within a same plane as the conductive elements and laterally spaced therefrom, the at least one routing trace connecting a first internal circuit component to a second internal circuit component of the semiconductor chip.

16. The semiconductor device of claim 15, wherein the area of the at least one active surface lying within the same plane as the plurality of conductive elements extends substantially an entire length of the semiconductor chip.

17. The semiconductor device of claim 15, wherein at least one of the at least one routing trace is configured to interconnect at least two otherwise electrically isolated internal circuitry components of the semiconductor chip.

18. The semiconductor device of claim 17, wherein the at least two otherwise electrically isolated internal circuitry components lie substantially within the same plane, and further comprising a third internal circuit component disposed between the at least two otherwise electrically isolated internal circuitry components.

19. The semiconductor device of claim 15, wherein the at least one routing trace is configured as a repair mechanism, the repair mechanism adapted to be operable by severance of the at least one routing trace to activate a selected internal circuit in the semiconductor chip.

20. The semiconductor device of claim 15, wherein the at least one routing trace is configured to be a repair mechanism, the repair mechanism adapted to be operable by severance of the at least one routing trace to deactivate a selected internal circuit in the semiconductor chip.

21. A semiconductor device, comprising:

a plurality of semiconductor chips, each having at least one active surface;

a plurality of conductive elements over the at least one active surface of each semiconductor chip of the plurality for directing signals between internal circuitry of a respective the semiconductor chip and at least one other external component;

at least one routing trace on an area of the at least one active surface unoccupied by the conductive elements of one of the plurality of semiconductor chips and extending to the area of the at least one active surface unoccupied by the conductive elements of another of the plurality of semiconductor chips to effect an electrical connection between at least one internal circuit component of the one of the plurality of semiconductor chips and the at least one internal circuit component of the another of the plurality of semiconductor chips.

22. The semiconductor device of claim 21, further including:

a carrier having a surface with at least one recess therein to receive the plurality of semiconductor chips, wherein the at least one recess allows substantial alignment of the surface of the carrier with the at least one active surface of the plurality of semiconductor chips.

23. The semiconductor device of claim 22, further including:

a filler material disposed in gaps between walls of each of the at least one recess and each of the plurality of semiconductor chips disposed therein.

24. The semiconductor device of claim 22, wherein the carrier includes a plurality of recesses.

25. A semiconductor device, comprising:

a semiconductor chip having at least one active surface;

a plurality of spaced apart conductive elements on the at least one active surface of the semiconductor chip for directing signals between internal circuitry of the semiconductor chip and at least one external component;

at least one routing trace extending between two circuit portions of the semiconductor chip, on an area of the at least one active surface unoccupied by the conductive elements, wherein the at least one routing trace comprises a repair mechanism.

26. The semiconductor device of claim 25, wherein the repair mechanism is configured to be operable by severance of the at least one routing trace to activate a selected internal circuit in the semiconductor chip.

27. The semiconductor device of claim 25, wherein the repair mechanism is configured to be operable by severance of the at least one routing trace to deactivate a selected internal circuit in the semiconductor chip.

28. A semiconductor device, comprising:

a semiconductor chip having at least one active surface;

a plurality of conductive elements within a common plane over the at least one active surface of the semiconductor chip, wherein each of the conductive elements is adapted to direct signals between internal circuitry of the semiconductor chip and at least one external component; and

at least one routing trace carried over an area of the at least one active surface and lying within the same plane as the conductive elements and laterally spaced therefrom, the at least one routing trace connecting a first internal circuit component to a second internal circuit component of the semiconductor chip.

29. A semiconductor device, comprising:

a semiconductor chip having at least one active surface;

a plurality of conductive elements over the at least one active surface of the semiconductor chip, wherein each of the conductive elements is adapted to direct signals between internal circuitry of the semiconductor chip and at least one external component; and

at least one routing trace carried over the at least one active surface in an area unoccupied by the conductive elements, the at least one routing trace connecting a first internal circuit component to a second internal circuit component of the semiconductor chip.

30. A semiconductor device, comprising:

a semiconductor chip having at least one active surface;

a plurality of conductive elements over the at least one active surface of the semiconductor chip, wherein each of the conductive elements is adapted to direct signals between internal circuitry of the semiconductor chip and at least one external component; and

at least one routing trace carried over an area of the at least one active surface in laterally spaced relationship to the conductive elements, the at least one routing trace connecting a first internal circuit component to a second internal circuit component of the semiconductor chip.