Offset peak current mode control circuit for multiple-phase power converter

• US 6,664,774 B2
• Filed: 03/27/2002
• Issued: 12/16/2003
• Est. Priority Date: 03/27/2002
• Status: Expired due to Fees

• Current Assignee: Semtech Corporation
• Original Assignee: Semtech Corporation
• Inventors: Lethellier, Patrice R.
• Primary Examiner(s): Berhane, Adolf D.
• Application Number:
  US10/112,010
• Publication Number:
  US 20030185024A1
• Time in Patent Office: 629 Days
• Field of Search: 363/65, 363/148, 363/149, 323/282, 323/284, 323/285, 323/351
• US Class Current: 323/282
• CPC Class Codes: H02J 1/102 being switching converters H02J1/108, H02J1/12 take precedence
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel

Abstract

An offset peak current mode control circuit is provided for use with a multiple-phase DC-to-DC voltage converter including a plurality of converter modules connected to a common load and having a common input voltage source, a current sensor coupled to a sensing resistor disposed in series between the common input voltage source and the load to derive a current sense signal corresponding to current passing through the sensing resistor, and a voltage error sensor coupled to the load to derive a voltage error signal corresponding to difference between an output voltage of the voltage converter and a reference voltage. When the DC-to-DC voltage converter is operated with a relatively low input voltage or a relatively high duty cycle resulting in an overlap of the current sense signal, the offset peak current mode control circuit utilizes information from the clean (i.e., non-overlapping) portion of the current sense signal, and then stretches the duty cycle applied to an associated voltage converter module so that it extends into the time of the overlapping portion of the current sense signal.

Claims

1. A multiple-phase DC-to-DC voltage converter comprising:

a plurality of converter modules connected to a common load and having a common input voltage source;

a current sensor coupled to a sensing resistor disposed in series between said common input voltage source and said load to derive a current sense signal corresponding to current passing through said sensing resistor;

a voltage error sensor coupled to said load to derive a voltage error signal corresponding to difference between an output voltage of said voltage converter and a reference voltage;

a plurality of current mode control circuits connected to respective ones of said plurality of converter modules, said current mode control circuits receiving said current sense signal and said voltage error signal, said current mode control circuit providing gate driving signals to said converter modules having a duty cycle determined by said current sense signal and said voltage error signal; and

a phase select circuit coupled to said plurality of current mode control circuits and alternately providing said plurality of current mode control circuits a phase select signal to initiate successive phases of operation within a power cycle;

wherein, when there is an overlap between adjacent ones of said successive phases, said current mode control circuits are operative to compare said current sense signal and said voltage error signal during a non-overlapping portion of a phase, and stretch a duration of said duty cycle of said gate driving signals to extend at least partially into an overlapping portion of said phase.

2. The multiple-phase DC-to-DC voltage converter of claim 1, wherein said current mode control circuits further comprise a pulse width modulator receiving said voltage error signal and said current sense signal, said pulse width modulator providing an output signal having an initial duty cycle having zero and non-zero portions.

3. The multiple-phase DC-to-DC voltage converter of claim 2, wherein said pulse width modulator further comprises a first comparator providing an output signal corresponding to a difference between said voltage error signal and said current sense signal, and a first latch connected to said first comparator and providing said output signal, wherein said output signal returns to said zero portion from said non-zero portion when said current sense signal exceeds said voltage error signal.

4. The multiple-phase DC-to-DC voltage converter of claim 2, wherein said current mode control circuits further comprise a capacitor coupled. to said pulse width modulator, said capacitor charging during said non-zero portion of said initial duty cycle and discharging during said zero portion of said initial duty cycle.

5. The multiple-phase DC-to-DC voltage converter of claim 4, wherein said current mode control circuits further comprise a second comparator providing an second output signal corresponding to a difference between a charge voltage of said capacitor and ground, and a second latch connected to said second comparator and providing said gate driving signals.

6. The multiple-phase DC-to-DC voltage converter of claim 1, further comprising a disabling circuit adapted to restore an initial duration of said duty cycle of said gate driving signals when there is no overlap between adjacent ones of said successive phases.

7. The multiple-phase DC-to-DC voltage converter of claim 1, wherein said plurality of converter modules further comprises three converter modules.

8. In a multiple-phase DC-to-DC voltage converter comprising a plurality of converter modules connected to a common load and having a common input voltage source, a method for providing current mode control of one of said plurality of converter modules when there is an overlap between adjacent phases of operation of said plurality of converter modules comprises the steps of:

sensing output current delivered to said common load to thereby determine a current sense signal representative of the current, said current sense signal comprising a clean portion prior to the overlap and a distorted portion during the overlap;

sensing output voltage across said common load to thereby determine a voltage error signal representative of a difference between the output voltage and a reference;

comparing said current sense signal with said voltage error signal during said clean portion of said current sense signal to thereby generate an intermediate gate driving signal;

stretching said intermediate gate driving signal to provide a final gate drive signal; and

controlling operation of said one of said converter modules using said final gate drive signal.

9. The method of claim 8, further comprising alternately providing one of said plurality of current mode control circuits with said final gate drive signal.

10. The method of claim 8, wherein said stretching step further comprises charging a capacitor during a non-zero portion of said intermediate gate driving signal and discharging said capacitor during a zero portion of said intermediate gate driving signal.

11. The method of claim 8, wherein said stretching step further comprises doubling a pulse width of said intermediate gate driving signal.

12. The method of claim 8, wherein said first sensing step further comprises measuring a voltage across a sensing resistor connected in series between said common load and said common input voltage source.

13. The method of claim 8, further comprising controlling operation of said one of said converter modules using said intermediate gate drive signal when there is no overlap between adjacent ones of said successive phases.

14. A current mode control circuit for use in a multiple-phase DC-to-DC voltage converter comprising a plurality of converter modules connected to a common load and having a common input voltage source, a current sensor coupled to a sensing resistor disposed in series between said common input voltage source and said load to derive a current sense signal corresponding to current passing through said sensing resistor, a voltage error sensor coupled to said load to derive a voltage error signal corresponding to difference between an output voltage of said voltage converter and a reference voltage, said current mode control circuit providing gate driving signals to an associated one of said converter modules having a duty cycle determined by said current sense signal and said voltage error signal, said current mode control circuit comprising:

means for comparing said current sense signal and said voltage error signal during a non-overlapping portion of a phase; and

means for stretching a duration of said duty cycle of said gate driving signals to extend at least partially into an overlapping portion of said phase.

15. The current mode control circuit of claim 14, wherein said comparing means further comprises a pulse width modulator receiving said voltage error signal and said current sense signal, said pulse width modulator providing an output signal having an initial duty cycle having zero and non-zero portions.

16. The current mode control circuit of claim 15, Wherein said pulse width modulator further comprises a first comparator providing an output signal corresponding to a difference between said voltage error signal and said current sense signal, and a first latch connected to said first comparator and providing said output signal, wherein said output signal returns to said zero portion from said non-zero portion when said current sense signal exceeds said voltage error signal.

17. The current mode control circuit of claim 15, wherein said stretching means further comprises a capacitor coupled to said pulse width modulator, said capacitor charging during said non-zero portion of said initial duty cycle and discharging during said zero portion of said initial duty cycle.

18. The current mode control circuit of claim 17, wherein said stretching means further comprises a second comparator providing an second output signal corresponding to a difference between a charge voltage of said capacitor and ground, and a second latch connected to said second comparator and providing said gate driving signals.

19. The current mode control circuit of claim 14, further comprising means for restoring an initial duration of said duty cycle of said gate driving signals when there is no overlap between adjacent ones of said successive phases.

20. The current mode control circuit of claim 14, further comprising means for synchronously initiating operation of said comparing and stretching means at a start of one of said successive phases.