Apparatus and method for generating a compensated percent-of-clock period delay signal

• US 6,664,838 B1
• Filed: 03/08/2002
• Issued: 12/16/2003
• Est. Priority Date: 08/31/2001
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Talledo, Cesar A.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): COX, CASSANDRA F
• Application Number:
  US10/094,101
• Time in Patent Office: 648 Days
• Field of Search: 327/158, 327/276, 327/273, 327/277, 327/279, 327/284, 327/286
• US Class Current: 327/277
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03K 5/06 by the use of delay lines or other analogue delay elements
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals

Abstract

An apparatus and method for generating a compensated percent-of-clock period delay signal are described. A first circuit determines how many delay elements a clock signal passes through during one period of the clock signal. A second circuit passes a signal to be delayed through the same number of delay elements according to information received from the first circuit. The ratio of the values of delay elements in the first and second circuits determines the percent-of-clock period that the passed signal is delayed. Since the clock signal is relatively insensitive to reference voltage and temperature variations as compared to the delay elements, the percent-of-clock period is maintained as more or less delay elements are passed through during a period of the clock signal.

Claims

1. An apparatus for generating a compensated percent-of-clock period delayed signal, comprising:

a first circuit generating an output indicative of a number of a first plurality of serially coupled delay elements individually having substantially a first delay value and together providing a combined delay related to a period of a clock signal, wherein said clock signal is relatively insensitive to reference voltage and temperature variations and said number varies according to said reference voltage and said temperature variations; and

a second circuit coupled to said first circuit and generating a delayed signal by passing a signal to be delayed through a second plurality of serially coupled delay elements individually having substantially a second delay value and together related in number to said number of said first plurality of serially coupled delay elements, wherein said signal to be delayed is a data strobe signal received from a DDR SDRAM and said delayed signal is employed for capturing at least one data signal provided by said DDR SDRAM.

2. The apparatus according to claim 1, wherein said combined delay is approximately equal to said period of said clock signal.

3. The apparatus according to claim 1, wherein a second number of said second plurality of serially coupled delay elements is equal to said number of said first plurality of serially coupled delay elements, and a ratio of said first delay value and said second delay value determines how much said delayed signal is delayed from said signal to be delayed as a percent of said period of said clock signal.

4. The apparatus according to claim 1, wherein said first delay value and said second delay value are equal, and a ratio of said number of said first plurality of serially coupled delay elements and a number of said second plurality of serially coupled delay elements determines how much said delayed signal is delayed from said signal to be delayed as a percent of said period of said clock signal.

5. The apparatus according to claim 1, wherein said number of said first plurality of serially coupled delay elements, a number of said second plurality of serially coupled delay elements, said first delay value, and said second delay value are selected such that said delayed signal is delayed from said signal by approximately twenty percent of said period of said clock signal.

6. The apparatus according to claim 1, wherein said first circuit comprises:

a first plurality of delay branches sequentially configured so as to have increasingly larger numbers of delay elements of said first delay value, said first plurality of delay branches including said first plurality of serially coupled delay elements and individually having an output and an input receiving said clock signal; and

a first register enabled by said clock signal and having inputs and outputs, said inputs of said first register coupled to corresponding outputs of said first plurality of delay branches such that said outputs of said first register are indicative of said number of said first plurality of serially coupled delay elements.

7. The apparatus according to claim 6, wherein said first circuit further comprises a second register enabled by said clock signal, said second register having inputs and outputs, said inputs of said second register coupled to corresponding outputs of said-first register so that said outputs of said second register are as or more accurately indicative of said number of said first plurality of serially coupled delay elements than said outputs of said first register.

8. The apparatus according to claim 7, wherein said first circuit further comprises a buffer having an input and an output, wherein said buffer input is coupled to said clock signal and said buffer output provides said clock signal to enable said second register.

9. The apparatus according to claim 8, wherein said first circuit further comprises delay control logic receiving and processing said outputs of said second register so as to provide information indicative of said number of said first plurality of serially coupled delay elements to said second circuit.

10. The apparatus according to claim 9, wherein said output of said second register defines a vector having bits among which a first positive edge transition is indicated where a first set of said bits on one side of said edge transition are mostly a first logic state and a second set of said bits on an opposite side of said edge transition are mostly a second logic state so that said number of said first plurality of serially coupled delay elements is indicated by a position of said first positive edge transition in said vector.

11. The apparatus according to claim 10, wherein said delay control logic has a first function of finding said position of said first positive edge transition in said vector.

12. The apparatus according to claim 11, wherein said delay control logic has a second function of adjusting said position of said first positive edge transition in said vector according to at least one previously found position so as to avoid abrupt changes in positions of edge transitions for adjacent periods of said clock signal.

13. The apparatus according to claim 12, wherein said delay control logic performs said second-function using a moving average technique.

14. The apparatus according to claim 1, wherein said second circuit comprises:

a second plurality of delay branches sequentially configured so as to have increasingly larger numbers of delay elements of said second delay value, said second plurality of delay branches including said second plurality of delay elements and individually having an output and an input receiving said signal to be delayed; and

a multiplexer having data inputs, a selector input, and an output, wherein said data inputs of said multiplexer are coupled to corresponding outputs of said second plurality of delay branches, said selector input is coupled to said output of said first circuit, and said output of said multiplexer provides said delayed signal.

15. A method for generating a compensated percent-of-clock period delayed signal, comprising:

determining a first number of serially coupled first delay elements having a combined delay substantially equal to a period of a clock signal, wherein said clock signal is relatively insensitive to reference voltage and temperature variations compared to individual of said serially coupled first delay elements; and

generating a delayed signal by passing a signal through a second number of serially coupled second delay elements, wherein said signal is a data strobe signal received from a DDR SDRAM, said second number is determined from said first number, and said delayed signal is employed for capturing at least one data signal provided by said DDR SDRAM and is delayed from said signal by a percentage of said period of said clock signal according to values of said first number, said second number, said first delay elements, and said second delay elements.

16. The method according to claim 15, wherein said determining a first number of serially coupled first delay elements having a combined delay substantially equal to a period of a clock, comprises:

providing said clock signal to a first delay tree having branches sequentially configured so as to have increasing numbers of serially coupled first delay elements; and

providing outputs of said branches of said first delay tree to a first register enabled by said clock signal and having an output indicative of said number of serially coupled first delay elements.

17. The method according to claim 16, wherein said determining a first number of serially coupled first delay elements having a combined delay approximately equal to a period of a clock signal, further comprises providing said output of said first register to a second register enabled by said clock signal and having an output generally more accurately indicative of said number of serially coupled first delay elements than said output of said first register.

18. The method according to claim 15, further comprising determining said second number of serially coupled second delay elements by processing a vector corresponding to said first number of serially coupled first delay elements, wherein said vector has bits among which a first positive edge transition is indicated where a first set of said bits on one side of said edge transition are mostly a first logic state and a second set of said bits on an opposite side of said edge transition are mostly a second logic state so that said number of said serially coupled first delay elements is indicated by a position of said first positive edge transition in said vector.

19. The method according to claim 18, wherein said processing of said vector corresponding to said first number of serially coupled first delay elements, comprises finding said position of said first positive edge transition in said vector.

20. The method according to claim 19, wherein said determining a first number of serially coupled first delay elements having a combined delay approximately equal to a period of a clock signal, and said generating a delayed signal by passing a received signal through a second number of serially coupled second delay elements are performed for each period of said clock signal.

21. The method according to claim 20, wherein said processing of said vector corresponding to said first number of serially coupled first delay elements, further comprises adjusting said found position of said first positive edge transition in said vector according to at least one previously found position so as to avoid abrupt changes in positions of first positive edge transitions between adjacent periods of said clock signal.

22. The method according to claim 21, wherein adjusting said found position of said first positive edge transition in said vector according to at least one previously found position so as to avoid abrupt changes in positions of first positive edge transitions between adjacent periods of said clock signal, comprises computing a moving average of such first positive edge transitions.

23. The method according to claim 15, wherein said generating a delayed signal by passing a signal through a second number of serially coupled second delay elements, comprises:

providing said signal to a second delay tree having delay branches sequentially configured so as to have increasing numbers of serially coupled second delay elements; and

providing outputs of said branches of said second delay tree to a multiplexer that provides said delayed signal according to information indicative of said first number of said serially coupled first delay elements.

24. An apparatus for generating a compensated percent-of-clock period delayed signal, comprising:

a first delay tree sensitive to reference voltage and temperature variations and having branches receiving and delaying by varying amounts a clock signal relatively insensitive to said reference voltage and said temperature variations as compared to said first delay tree;

a processing circuit capturing outputs of said first delay tree in response to said clock signal so as to indicate a first set of branches of said first delay tree through which a previously generated positive edge of said clock signal has passed through and a second set of branches of said first delay tree through which said previously generated positive edge of said clock signal has not passed through during a period of said clock signal;

a second delay tree similarly sensitive to said reference voltage and said temperature variations as compared to said first delay tree, and having branches receiving and delaying by varying amounts a signal to be delayed; and

a selection circuit selecting an output of one of said branches of said second delay tree to provide a delayed signal compensated for said reference voltage and said temperature variations according to information of said captured outputs of said first delay tree.

25. The apparatus according to claim 24, wherein said branches of said first delay tree are organized sequentially and configured such that each of said branches provides incrementally more delay than a previous branch in sequence.

26. The apparatus according to claim 25, wherein said each of said branches includes incrementally one more delay element than said previous branch in sequence.

27. The apparatus according to claim 25, wherein a first in sequence of said branches of said first delay tree receives said clock signal and delays it through a first delay element having a first delay value to provide a first branch output, and subsequent in sequence of said branches of said first delay tree are coupled to branch outputs of prior in sequence branches and delays signals received from such branch outputs through delay elements having said first delay value to generate branch outputs of said subsequent in sequence branches.

28. The apparatus according to claim 27, wherein said processing circuit comprises a first register having inputs coupled to corresponding outputs of branches of said first delay tree, and enabled by said clock signal.

29. The apparatus according to claim 28, wherein said processing circuit further comprises a second register having inputs coupled to corresponding outputs of said first register, and enabled by said clock signal.

30. The apparatus according to claim 29, wherein said processing circuit further comprises a buffer having an input coupled to said clock signal, and an output providing said clock signal to said second register.

31. The apparatus according to claim 30, wherein said processing circuit further comprises logic that is configured to find a first positive edge transition in said bits of said output of said second register, wherein such first positive edge transition has bits of one logic state on one side of said first positive edge transition and bits of another logic state on an opposite side of said first positive edge transition so as to indicate a branch of said delay tree having an approximately equal delay value as a period of said clock signal.

32. The apparatus according to claim 31, wherein said logic is further configured to adjust a position of said first positive edge transition according to at least one previously found position during a prior period of said clock signal so as to avoid abrupt changes in positions of said first positive edge transitions found between adjacent periods of said clock signal.

33. The apparatus according to claim 32, wherein said logic to adjust said position of said first positive edge transition according to a moving average of previously found positions during prior periods of said clock signal.

34. The apparatus according to claim 33, wherein said selection circuit comprises a multiplexer having inputs coupled to outputs of said second delay tree, and an output providing said delayed signal as selected by information generated by said logic of said processing circuit.

35. The apparatus according to claim 34, wherein said branches of said second delay tree are organized sequentially and configured such that each of said branches provides incremental more delay than a previous branch in sequence.

36. The apparatus according to claim 35, wherein a ratio of delays for corresponding branches of said first and said second delay trees determines a delay that said signal to be delayed is delayed as a percent of said period of said clock signal.

37. An apparatus for generating a compensated percent-of-clock period delayed signal, comprising:

a first circuit generating an output indicative of a number of a first plurality of serially coupled delay elements individually having substantially a first delay value and together providing a combined delay related to a period of a clock signal, wherein said clock signal is relatively insensitive to reference voltage and temperature variations and said number varies according to said reference voltage and said temperature variations, and wherein said first circuit includes a first plurality of delay branches and a first register, said first plurality of delay branches sequentially configured so as to have increasingly larger numbers of delay elements of said first delay value, said first plurality of delay branches including said first plurality of serially coupled delay elements and individually having an output and an input receiving said clock signal, and said first register enabled by said clock signal and having inputs and outputs, said inputs of said first register coupled to corresponding outputs of said first plurality of delay branches such that said outputs of said first register are indicative of said number of said first plurality of serially coupled delay elements; and

a second circuit coupled to said first circuit and generating a delayed signal by passing a signal to be delayed through a second plurality of serially coupled delay elements individually having substantially a second delay value and together related in number to said number of said first plurality of serially coupled delay elements.

38. The apparatus according to claim 37, wherein said first circuit further comprises a second register enabled by said clock signal, said second register having inputs and outputs, said inputs of said second register coupled to corresponding outputs of said first register so that said outputs of said second register are as or more accurately indicative of said number of said first plurality of serially coupled delay elements than said outputs of said first register.

39. The apparatus according to claim 38, wherein said first circuit further comprises a buffer having an input and an output, wherein said buffer input is coupled to said clock signal and said buffer output provides said clock signal to enable said second register.

40. The apparatus according to claim 39, wherein said first circuit further comprises delay control logic receiving and processing said outputs of said second register so as to provide information indicative of said number of said first plurality of serially coupled delay elements to said second circuit.

41. A The apparatus according to claim 40, herein said output of said second register defines a vector having bits among which a first positive edge transition is indicated where a first set of said bits on one side of said edge transition are mostly a first logic state and a second set of said bits on an opposite side of said edge transition are mostly a second logic state so that said number of said first plurality of serially coupled delay elements is indicated by a position of said first positive edge transition in said vector.

42. The apparatus according to claim 41, wherein said delay control logic has a first function of finding said position of said first positive edge transition in said vector.

43. The apparatus according to claim 42, wherein said delay control logic has a second function of adjusting said position of said first positive edge transition in said vector according to at least one previously found position so as to avoid abrupt changes in positions of edge transitions for adjacent periods of said clock signal.

44. The apparatus according to claim 43, wherein said delay control logic performs said second function using a moving average technique.

45. The apparatus according to claim 37, wherein said second circuit comprises:

a second plurality of delay branches sequentially configured so as to have increasingly larger numbers of delay elements of said second delay value, said second plurality of delay branches including said second plurality of delay elements and individually having an output and an input receiving said signal to be delayed; and

a multiplexer having data inputs, a selector input, and an output, wherein said data inputs of said multiplexer are coupled to corresponding outputs of said second plurality of delay branches, said selector input is coupled to said output of said first circuit, and said output of said multiplexer provides said delayed signal.

46. An apparatus for generating a compensated percent-of-clock period delayed signal, comprising:

a first circuit generating an output indicative of a number of a first plurality of serially coupled delay elements individually having substantially a first delay value and together providing a combined delay related to a period of a clock signal, wherein said clock signal is relatively insensitive to reference voltage and temperature variations and said number varies according to said reference voltage and said temperature variations; and

a second circuit coupled to said first circuit and generating a delayed signal by passing a signal to be delayed through a second plurality of serially coupled delay elements individually having substantially a second delay value and together related in number to said number of said first plurality of serially coupled delay elements, wherein said second circuit includes a second plurality of delay branches and a multiplexer, said second plurality of delay branches sequentially configured so as to have increasingly larger numbers of delay elements of said second delay value, said second plurality of delay branches including said second plurality of delay elements and individually having an output and an input receiving said signal to be delayed, and said multiplexer having data inputs, a selector input, and an output, wherein said data inputs of said multiplexer are coupled to corresponding outputs of said second plurality of delay branches, said selector input is coupled to said output of said first circuit, and said output of said multiplexer provides said delayed signal.

47. A method for generating a compensated percent-of-clock period delayed signal, comprising:

determining a first number of serially coupled first delay elements having a combined delay substantially equal to a period of a clock signal, wherein said clock signal is relatively insensitive to reference voltage and temperature variations compared to individual of said serially coupled first delay elements, and said determining includes providing said clock signal to a first delay tree having branches sequentially configured so as to have increasing numbers of serially coupled first delay elements, and providing outputs of said branches of said first delay tree to a first register enabled by said clock signal and having an output indicative of said number of serially coupled first delay elements; and

generating a delayed signal by passing a signal through a second number of serially coupled second delay elements, wherein said second number is determined from said first number and said delayed signal is delayed from said signal by a percentage of said period of said clock signal according to values of said first number, said second number, said first delay elements, and said second delay elements.

48. The method according to claim 47, wherein said determining a first number of serially coupled first delay elements having a combined delay approximately equal to a period of a clock signal, further comprises providing said output of said first register to a second register enabled by said clock signal and having an output generally more accurately indicative of said number of serially coupled first delay elements than said output of said first register.

49. A method for generating a compensated percent-of-clock period delayed signal, comprising:

determining a first number of serially coupled first delay elements having a combined delay substantially equal to a period of a clock signal, wherein said clock signal is relatively insensitive to reference voltage and temperature variations compared to individual of said serially coupled first delay elements; and

generating a delayed signal by passing a signal through a second number of serially coupled second delay elements, wherein said second number is determined from said first number by processing a vector corresponding to said first number and having bits among which a first positive edge transition is indicated where a first set of said bits on one side of said edge transition are mostly a first logic state and a second set of said bits on an opposite side of said edge transition are mostly a second logic state so that said first number is indicated by a position of said first positive edge transition in said vector, and said delayed signal is delayed from said signal by a percentage of said period of said clock signal according to values of said first number, said second number, said first delay elements, and said second delay elements.

50. The method according to claim 49, wherein said processing of said vector corresponding to said first number of serially coupled first delay elements, comprises finding said position of said first positive edge transition in said vector.

51. The method according to claim 50, wherein said determining a first number of serially coupled first delay elements having a combined delay approximately equal to a period of a clock signal, and said generating a delayed signal by passing a received signal through a second number of serially coupled second delay elements are performed for each period of said clock signal.

52. The method according to claim 51, wherein sad processing of said vector corresponding to said first number of serially coupled first delay elements, further comprises adjusting said found position of said first positive edge transition in said vector according to at least one previously found position so as to avoid abrupt changes in positions of first positive edge transitions between adjacent periods of said clock signal.

53. The method according to claim 52, wherein adjusting said found position of said first positive edge transition in said vector according to at least one previously found position so as to avoid abrupt changes in positions of first positive edge transitions between adjacent periods of said clock signal, comprises computing a moving average of such first positive edge transitions.

54. A method for generating a compensated percent-of-clock period delayed signal, comprising:

determining a first number of serially coupled first delay elements having a combined delay substantially equal to a period of a clock signal, wherein said clock signal is relatively insensitive to reference voltage and temperature variations compared to individual of said serially coupled first delay elements; and

generating a delayed signal by passing a signal through a second number of serially coupled second delay elements, wherein said second number is determined from said first number and said delayed signal is delayed from said signal by a percentage of said period of said clock signal according to values of said first number, said second number, said first delay elements, and said second delay elements, and said generating includes providing said signal to a second delay tree having delay branches sequentially configured so as to have increasing numbers of serially coupled second delay elements and providing outputs of said branches of said second delay tree to a multiplexer that provides said delayed signal according to information indicative of said first number of said serially coupled first delay elements.