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Apparatus and method for generating a compensated percent-of-clock period delay signal

  • US 6,664,838 B1
  • Filed: 03/08/2002
  • Issued: 12/16/2003
  • Est. Priority Date: 08/31/2001
  • Status: Active Grant
First Claim
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1. An apparatus for generating a compensated percent-of-clock period delayed signal, comprising:

  • a first circuit generating an output indicative of a number of a first plurality of serially coupled delay elements individually having substantially a first delay value and together providing a combined delay related to a period of a clock signal, wherein said clock signal is relatively insensitive to reference voltage and temperature variations and said number varies according to said reference voltage and said temperature variations; and

    a second circuit coupled to said first circuit and generating a delayed signal by passing a signal to be delayed through a second plurality of serially coupled delay elements individually having substantially a second delay value and together related in number to said number of said first plurality of serially coupled delay elements, wherein said signal to be delayed is a data strobe signal received from a DDR SDRAM and said delayed signal is employed for capturing at least one data signal provided by said DDR SDRAM.

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