CTAT generator using parasitic PNP device in deep sub-micron CMOS process

• US 6,664,847 B1
• Filed: 10/10/2002
• Issued: 12/16/2003
• Est. Priority Date: 10/10/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ye, Jing
• Primary Examiner(s): Cunningham, Terry D.
• Application Number:
  US10/268,174
• Time in Patent Office: 432 Days
• Field of Search: 327/538, 327/539, 327/540, 327/541, 327/543, 327/542, 323/312, 323/315
• US Class Current: 327/543
• CPC Class Codes: G05F 3/267 using both bipolar and field-effect technology

Abstract

A control circuit generates a current that remains substantially constant over temperature using a bandgap reference for providing a PTAT current. A first current mirror generates a current proportional to the PTAT current. A novel complementary to absolute temperature (CTAT) current source provides a CTAT current void of bipolar transistor base current, regardless of whether it is implemented in a CMOS digital process or not. It includes a first bias current source that connects to a first resistive circuit and a first subcircuit portion. The first subcircuit portion, including a first bipolar transistor, generates a current proportional to the base emitter voltage of the first bipolar transistor and the base current of the first bipolar transistor. A second bias current source connects to a second resistive circuit and a second subcircuit portion. The second subcircuit portion, including a second bipolar transistor, generates a current proportional to the base current of the second bipolar transistor. A second current mirror connects between the first subcircuit portion and the second subcircuit portion to subtract the base current of the first bipolar transistor and, thus, provide a CTAT current proportional to the first and second resistive circuits. A third current mirror connects between the second current mirror and the first current mirror such that the PTAT current and the CTAT current are summed together to provide current that remains substantially constant over temperature.

Claims

1. A control circuit for generating a current that remains substantially constant over temperature, comprising:

a proportional to absolute temperature (PTAT) current source that provides a PTAT current;

a first current mirror coupled to receive the PTAT current to generate a current proportional to the PTAT current;

a complementary to absolute temperature (CTAT) current source that provides a CTAT current, the CTAT current source coupled to the first current mirror to form an output node such that the current proportional to the PTAT current and the CTAT current are summed together to provide the current that remains substantially constant over temperature at the output node; and

wherein the CTAT current source comprises,

a first bias current source,

a first resistive circuit coupled to receive the first bias current,

a first subcircuit portion coupled to the first resistive circuit and the first bias current source, the first subcircuit portion, having a first bipolar transistor, coupled to receive the first bias current to generate a current proportional to the base emitter voltage of the first bipolar transistor and the base current of the first bipolar transistor,

a second bias current source,

a second resistive circuit coupled to receive the second bias current,

a second subcircuit portion coupled to the second resistive circuit and the second bias current source, second subcircuit portion, having a second bipolar transistor, coupled to receive the second bias current to generate a current proportional to the base current of the second bipolar transistor,

a second current mirror coupled between the first subcircuit portion and the second subcircuit portion to subtract the base current from the first subcircuit, and

a third current mirror coupled between the second current mirror and the first current mirror to provide the current that remains substantially constant over temperature.

2. A control circuit as recited in claim 1, wherein the PTAT current source is a bandgap reference circuit.

3. A control circuit as recited in claim 1, wherein the first current mirror comprises:

a first FET transistor, having a gate, a drain and a source, the drain and the gate coupled to receive the PTAT current, the source coupled to ground; and

a second FET transistor, having a gate, a drain and a source, the gate coupled to the gate of the first FET transistor, the source coupled to ground, the drain coupled to the output node to provide the current proportional to the PTAT current.

4. A control circuit as recited in claim 1, wherein the first subcircuit portion comprises:

a first bipolar transistor, having a base, a collector, and an emitter, the emitter coupled to receive the first bias current, the collector coupled to ground, the first resistive circuit coupled between the emitter and base of the first bipolar transistor; and

a first FET transistor having a gate, a drain, and a source, the source coupled to the base of the first bipolar transistor, the gate coupled to receive the bias voltage, the drain coupled to the second current source.

5. A control circuit as recited in claim 4, wherein the first resistive circuit is a resistor.

6. A control circuit as recited in claim 1, wherein the second subcircuit portion comprises:

a second bipolar transistor, having a base, a collector, and an emitter, the emitter coupled to receive the second bias current, the collector coupled to ground, the second resistive circuit coupled between the emitter of the second bipolar transistor and base of the first bipolar transistor; and

a second FET transistor having a gate, a drain, and a source, the source coupled to the base of the second bipolar transistor, the gate coupled to receive the bias voltage, the drain coupled to the second current mirror.

7. A control circuit as recited in claim 6, wherein the second resistive circuit is a resistor.

8. A control circuit as recited in claim 1, wherein the second current mirror comprises:

a first FET transistor, having a gate, a drain and a source, the drain and the gate coupled to the second subcircuit portion, the source coupled to ground; and

a second FET transistor, having a gate, a drain and a source, the drain coupled to the first subcircuit portion, the gate coupled to the gate of the first FET transistor, the source coupled to ground.

9. A control circuit as recited in claim 1, wherein the third current mirror comprises:

a first FET transistor, having a gate, a drain and a source, the drain and the gate coupled to the first subcircuit portion, the source coupled to ground; and

a second FET transistor, having a gate, a drain and a source, the drain coupled to the output node, the gate coupled to the gate of the first FET transistor, the source coupled to ground.

10. A method of generating a current that remains substantially constant over temperature from a bandgap reference voltage, comprising the steps of:

a. providing a proportional to absolute temperature (PTAT) current;

b. receiving the PTAT current by a first current mirror to provide a current proportional to the PTAT current;

c. providing a first bias current;

d. receiving the first bias current by a first transistor having a base, an emitter and a collector, the emitter coupled to receive the first bias current, the collector coupled to ground, and in accordance therewith providing a first base-emitter voltage and a first base current;

e. receiving the first bias current by a first resistive circuit coupled between the base and emitter of the first transistor and in accordance therewith providing a current proportional to the base-emitter voltage of the first transistor;

f. providing a second bias current;

g. receiving the second bias current by a second transistor having a base, an emitter and a collector, the emitter coupled to receive the second bias current, the collector coupled to ground, and in accordance therewith providing a second base-emitter voltage and a second base current;

h. receiving the second bias current by a second resistive circuit coupled between the emitter of the second transistor and the base of the first transistor and in accordance therewith providing a current proportional to the base-emitter voltage of the second transistor, the current provided by the first resistive circuit equals the current provided by the second resistive circuit;

i. providing a bias voltage;

j. receiving the bias voltage by a third and fourth transistor having a gate, a drain, and a source, the gate of the third and fourth transistor coupled to receive the bias voltage, the source of the third transistor coupled to the base of the first transistor, the source of the fourth transistor coupled to the base of the second transistor;

k. receiving the current provided by to the first and second resistive circuit and first and second base current by a second current mirror, the first and second base current are equal and oppose such that the second base current eliminates the first base current, and in accordance therewith providing a current complementary to absolute temperature (CTAT);

l. adjusting the first current mirror such that the slope with respect to temperature of the PTAT current is equal in magnitude and opposite in sign to the slope with respect to temperature of the CTAT current; and

m. combining the PTAT and CTAT currents using a third current mirror coupled between the first and the second current mirrors to provide a current that remains substantially constant over temperature.